+/** @file\r
+ Functions for accessing I2C registers.\r
+ \r
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution. \r
+ The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php. \r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ \r
+--*/\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <PchRegs/PchRegsPcu.h> \r
+#include <PchRegs.h>\r
+#include <PlatformBaseAddresses.h>\r
+#include <PchRegs/PchRegsLpss.h> \r
+#include <Library/I2CLib.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <I2CRegs.h>\r
+\r
+#define GLOBAL_NVS_OFFSET(Field) (UINTN)((CHAR8*)&((EFI_GLOBAL_NVS_AREA*)0)->Field - (CHAR8*)0)\r
+\r
+#define PCIEX_BASE_ADDRESS 0xE0000000\r
+#define PCI_EXPRESS_BASE_ADDRESS ((VOID *) (UINTN) PCIEX_BASE_ADDRESS)\r
+#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
+ ((UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
+ (UINTN)(Bus << 20) + \\r
+ (UINTN)(Device << 15) + \\r
+ (UINTN)(Function << 12) + \\r
+ (UINTN)(Register) \\r
+ )\r
+#define PCI_D31F0_REG_BASE PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
+\r
+typedef struct _LPSS_PCI_DEVICE_INFO {\r
+ UINTN Segment;\r
+ UINTN BusNum;\r
+ UINTN DeviceNum;\r
+ UINTN FunctionNum;\r
+ UINTN Bar0;\r
+ UINTN Bar1;\r
+} LPSS_PCI_DEVICE_INFO;\r
+\r
+LPSS_PCI_DEVICE_INFO mLpssPciDeviceList[] = {\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1, PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC, 0xFE900000, 0xFE908000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0, 0xFE910000, 0xFE918000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1, 0xFE920000, 0xFE928000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2, 0xFE930000, 0xFE938000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3, 0xFE940000, 0xFE948000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4, 0xFE950000, 0xFE958000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5, 0xFE960000, 0xFE968000},\r
+ {0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6, 0xFE970000, 0xFE978000}\r
+};\r
+\r
+#define LPSS_PCI_DEVICE_NUMBER sizeof(mLpssPciDeviceList)/sizeof(LPSS_PCI_DEVICE_INFO)\r
+\r
+STATIC UINTN mI2CBaseAddress = 0;\r
+STATIC UINT16 mI2CSlaveAddress = 0;\r
+\r
+UINT16 mI2cMode=B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE ;\r
+\r
+UINTN mI2cNvsBaseAddress[] = {\r
+ GLOBAL_NVS_OFFSET(LDMA2Addr),\r
+ GLOBAL_NVS_OFFSET(I2C1Addr),\r
+ GLOBAL_NVS_OFFSET(I2C2Addr),\r
+ GLOBAL_NVS_OFFSET(I2C3Addr),\r
+ GLOBAL_NVS_OFFSET(I2C4Addr),\r
+ GLOBAL_NVS_OFFSET(I2C5Addr),\r
+ GLOBAL_NVS_OFFSET(I2C6Addr),\r
+ GLOBAL_NVS_OFFSET(I2C7Addr)\r
+ };\r
+\r
+/**\r
+ This function get I2Cx controller base address (BAR0).\r
+\r
+ @param I2cControllerIndex Bus Number of I2C controller.\r
+\r
+ @return I2C BAR. \r
+**/\r
+UINTN\r
+GetI2cBarAddr(\r
+ IN UINT8 I2cControllerIndex\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;\r
+ UINTN AcpiBaseAddr;\r
+ UINTN PciMmBase=0;\r
+\r
+ ASSERT(gBS!=NULL);\r
+\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiGlobalNvsAreaProtocolGuid,\r
+ NULL,\r
+ &GlobalNvsArea\r
+ );\r
+ \r
+ //\r
+ // PCI mode from PEI ( Global NVS is not ready).\r
+ //\r
+ if (EFI_ERROR(Status)) {\r
+ DEBUG ((EFI_D_INFO, "GetI2cBarAddr() gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));\r
+ //\r
+ // Global NVS is not ready.\r
+ //\r
+ return 0;\r
+ }\r
+\r
+ AcpiBaseAddr = *(UINTN*)((CHAR8*)GlobalNvsArea->Area + mI2cNvsBaseAddress[I2cControllerIndex + 1]);\r
+ \r
+ //\r
+ //PCI mode from DXE (global NVS protocal) to LPSS OnReadytoBoot(swith to ACPI).\r
+ //\r
+ if(AcpiBaseAddr==0) {\r
+ PciMmBase = MmPciAddress (\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].Segment,\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].BusNum,\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum,\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum,\r
+ 0\r
+ );\r
+ DEBUG((EFI_D_ERROR, "\nGetI2cBarAddr() I2C Device %x %x %x PciMmBase:%x\n", \\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].BusNum, \\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum, \\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum, PciMmBase));\r
+\r
+ if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {\r
+ if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {\r
+ //\r
+ // Get the address allocted.\r
+ //\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR); \r
+ mLpssPciDeviceList[I2cControllerIndex + 1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);\r
+ }\r
+ }\r
+ AcpiBaseAddr =mLpssPciDeviceList[I2cControllerIndex+1].Bar0;\r
+ }\r
+ \r
+ //\r
+ // ACPI mode from BDS: LPSS OnReadytoBoot\r
+ //\r
+ else {\r
+ DEBUG ((EFI_D_INFO, "GetI2cBarAddr() NVS Varialable is updated by this LIB or LPSS \n"));\r
+ }\r
+ \r
+ DEBUG ((EFI_D_INFO, "GetI2cBarAddr() I2cControllerIndex+1 0x%x AcpiBaseAddr:0x%x \n", (I2cControllerIndex + 1), AcpiBaseAddr));\r
+ return AcpiBaseAddr;\r
+}\r
+\r
+\r
+/**\r
+ This function enables I2C controllers.\r
+\r
+ @param I2cControllerIndex Bus Number of I2C controllers.\r
+\r
+ @return Result of the I2C initialization.\r
+**/\r
+EFI_STATUS\r
+ProgramPciLpssI2C (\r
+ IN UINT8 I2cControllerIndex\r
+ )\r
+{\r
+ UINT32 PmcBase;\r
+ UINTN PciMmBase=0;\r
+ EFI_STATUS Status;\r
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;\r
+\r
+ UINT32 PmcFunctionDsiable[]= {\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1,\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2,\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3,\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4,\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5,\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6,\r
+ B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7\r
+ };\r
+\r
+ DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Start\n"));\r
+\r
+ //\r
+ // Set the VLV Function Disable Register to ZERO\r
+ //\r
+ PmcBase = MmioRead32 (PCI_D31F0_REG_BASE + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;\r
+ if(MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)&PmcFunctionDsiable[I2cControllerIndex]) {\r
+ DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End:I2C[%x] is disabled\n",I2cControllerIndex));\r
+ return EFI_NOT_READY;\r
+ }\r
+ \r
+ DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C()------------I2cControllerIndex=%x,PMC=%x\n",I2cControllerIndex,MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)));\r
+\r
+ {\r
+ PciMmBase = MmPciAddress (\r
+ mLpssPciDeviceList[I2cControllerIndex+1].Segment,\r
+ mLpssPciDeviceList[I2cControllerIndex+1].BusNum,\r
+ mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum,\r
+ mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum,\r
+ 0\r
+ );\r
+ \r
+ DEBUG((EFI_D_ERROR, "Program Pci Lpss I2C Device %x %x %x PciMmBase:%x\n", \\r
+ mLpssPciDeviceList[I2cControllerIndex+1].BusNum, \\r
+ mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum, \\r
+ mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum, PciMmBase));\r
+\r
+ if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {\r
+ if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {\r
+ //\r
+ // Get the address allocted.\r
+ //\r
+ mLpssPciDeviceList[I2cControllerIndex+1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR); \r
+ mLpssPciDeviceList[I2cControllerIndex+1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);\r
+ DEBUG((EFI_D_ERROR, "ProgramPciLpssI2C() bar0:0x%x bar1:0x%x\n",mLpssPciDeviceList[I2cControllerIndex+1].Bar0, mLpssPciDeviceList[I2cControllerIndex+1].Bar1));\r
+ } else {\r
+ \r
+ //\r
+ // Program BAR 0\r
+ //\r
+ ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA) == mLpssPciDeviceList[I2cControllerIndex+1].Bar0) && (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 != 0));\r
+ MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA));\r
+ \r
+ //\r
+ // Program BAR 1\r
+ //\r
+ ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA) == mLpssPciDeviceList[I2cControllerIndex+1].Bar1) && (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 != 0));\r
+ MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR1), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA));\r
+ \r
+ //\r
+ // Bus Master Enable & Memory Space Enable\r
+ //\r
+ MmioOr32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_STSCMD), (UINT32) (B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE));\r
+ ASSERT (MmioRead32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0) != 0xFFFFFFFF);\r
+ }\r
+ \r
+ //\r
+ // Release Resets\r
+ //\r
+ MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPIO_I2C_MEM_RESETS,(B_PCH_LPIO_I2C_MEM_RESETS_FUNC | B_PCH_LPIO_I2C_MEM_RESETS_APB));\r
+ \r
+ //\r
+ // Activate Clocks\r
+ //\r
+ MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPSS_I2C_MEM_PCP,0x80020003);//No use for A0\r
+\r
+ DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Programmed()\n"));\r
+ }\r
+ \r
+ //\r
+ // BDS: already switched to ACPI mode\r
+ //\r
+ else {\r
+ ASSERT(gBS!=NULL);\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiGlobalNvsAreaProtocolGuid,\r
+ NULL,\r
+ &GlobalNvsArea\r
+ );\r
+ if (EFI_ERROR(Status)) {\r
+ DEBUG ((EFI_D_INFO, "GetI2cBarAddr() gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));\r
+ //\r
+ // gEfiGlobalNvsAreaProtocolGuid is not ready.\r
+ //\r
+ return 0;\r
+ }\r
+ mLpssPciDeviceList[I2cControllerIndex + 1].Bar0 = *(UINTN*)((CHAR8*)GlobalNvsArea->Area + mI2cNvsBaseAddress[I2cControllerIndex + 1]);\r
+ DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C(): is switched to ACPI 0x:%x \n",mLpssPciDeviceList[I2cControllerIndex + 1].Bar0));\r
+ }\r
+ }\r
+ \r
+ DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End\n"));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Disable I2C Bus.\r
+\r
+ @param VOID.\r
+\r
+ @return Result of the I2C disabling.\r
+**/\r
+RETURN_STATUS\r
+I2cDisable (\r
+ VOID\r
+ )\r
+{ \r
+ //\r
+ // 0.1 seconds\r
+ //\r
+ UINT32 NumTries = 10000;\r
+ \r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_ENABLE, 0 );\r
+ while ( 0 != ( MmioRead32 ( mI2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) {\r
+ MicroSecondDelay (10);\r
+ NumTries --;\r
+ if(0 == NumTries) {\r
+ return RETURN_NOT_READY;\r
+ }\r
+ }\r
+ \r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Enable I2C Bus.\r
+\r
+ @param VOID.\r
+\r
+ @return Result of the I2C disabling.\r
+**/\r
+RETURN_STATUS\r
+I2cEnable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // 0.1 seconds\r
+ //\r
+ UINT32 NumTries = 10000;\r
+ \r
+ MmioWrite32 (mI2CBaseAddress + R_IC_ENABLE, 1);\r
+ \r
+ while (0 == (MmioRead32 (mI2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) {\r
+ MicroSecondDelay (10);\r
+ NumTries --;\r
+ if(0 == NumTries){\r
+ return RETURN_NOT_READY;\r
+ }\r
+ }\r
+ \r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Enable I2C Bus.\r
+\r
+ @param VOID.\r
+\r
+ @return Result of the I2C enabling.\r
+**/\r
+RETURN_STATUS\r
+I2cBusFrequencySet (\r
+ IN UINTN BusClockHertz\r
+ )\r
+{\r
+ DEBUG((EFI_D_INFO,"InputFreq BusClockHertz: %d\r\n",BusClockHertz));\r
+ \r
+ //\r
+ // Set the 100 KHz clock divider according to SV result and I2C spec\r
+ //\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 );\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 );\r
+ \r
+ //\r
+ // Set the 400 KHz clock divider according to SV result and I2C spec\r
+ //\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 );\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD );\r
+\r
+ switch ( BusClockHertz ) {\r
+ case 100 * 1000:\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x40);//100K\r
+ mI2cMode = V_SPEED_STANDARD;\r
+ break;\r
+ case 400 * 1000:\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x32);//400K\r
+ mI2cMode = V_SPEED_FAST;\r
+ break;\r
+ default:\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x09);//3.4M\r
+ mI2cMode = V_SPEED_HIGH;\r
+ }\r
+\r
+ //\r
+ // Select the frequency counter,\r
+ // Enable restart condition,\r
+ // Enable master FSM, disable slave FSM.\r
+ //\r
+ mI2cMode |= B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initializes the host controller to execute I2C commands.\r
+\r
+ @param I2cControllerIndex Index of I2C controller in LPSS device. 0 represents I2C0, which is PCI function 1 of LPSS device. \r
+ \r
+ @return EFI_SUCCESS Opcode initialization on the I2C host controller completed.\r
+ @return EFI_DEVICE_ERROR Device error, operation failed.\r
+**/\r
+EFI_STATUS\r
+I2CInit (\r
+ IN UINT8 I2cControllerIndex,\r
+ IN UINT16 SlaveAddress\r
+ )\r
+{\r
+ EFI_STATUS Status=RETURN_SUCCESS;\r
+ UINT32 NumTries = 0;\r
+ UINTN GnvsI2cBarAddr=0;\r
+ \r
+ //\r
+ // Verify the parameters\r
+ //\r
+ if ((1023 < SlaveAddress) || (6 < I2cControllerIndex)) {\r
+ Status = RETURN_INVALID_PARAMETER;\r
+ DEBUG((EFI_D_INFO,"I2CInit Exit with RETURN_INVALID_PARAMETER\r\n"));\r
+ return Status;\r
+ }\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );\r
+ mI2CSlaveAddress = SlaveAddress;\r
+\r
+ //\r
+ // 1.PEI: program and init ( before pci enumeration).\r
+ // 2.DXE:update address and re-init ( after pci enumeration).\r
+ // 3.BDS:update ACPI address and re-init ( after acpi mode is enabled).\r
+ //\r
+ if(mI2CBaseAddress == mLpssPciDeviceList[I2cControllerIndex + 1].Bar0) {\r
+ \r
+ //\r
+ // I2CInit is already called.\r
+ //\r
+ GnvsI2cBarAddr=GetI2cBarAddr(I2cControllerIndex);\r
+ \r
+ if((GnvsI2cBarAddr == 0)||(GnvsI2cBarAddr == mI2CBaseAddress)) {\r
+ DEBUG((EFI_D_INFO,"I2CInit Exit with mI2CBaseAddress:%x == [%x].Bar0\r\n",mI2CBaseAddress,I2cControllerIndex+1));\r
+ return RETURN_SUCCESS;\r
+ }\r
+ }\r
+ \r
+ Status=ProgramPciLpssI2C(I2cControllerIndex);\r
+ if(Status!=EFI_SUCCESS) {\r
+ return Status;\r
+ }\r
+\r
+\r
+ mI2CBaseAddress = (UINT32) mLpssPciDeviceList[I2cControllerIndex + 1].Bar0;\r
+ DEBUG ((EFI_D_ERROR, "mI2CBaseAddress = 0x%x \n",mI2CBaseAddress));\r
+ \r
+ //\r
+ // 1 seconds.\r
+ //\r
+ NumTries = 10000; \r
+ while ((1 == ( MmioRead32 ( mI2CBaseAddress + R_IC_STATUS) & STAT_MST_ACTIVITY ))) {\r
+ MicroSecondDelay(10);\r
+ NumTries --;\r
+ if(0 == NumTries) {\r
+ DEBUG((EFI_D_INFO, "Try timeout\r\n"));\r
+ return RETURN_DEVICE_ERROR;\r
+ }\r
+ }\r
+ \r
+ Status = I2cDisable();\r
+ DEBUG((EFI_D_INFO, "I2cDisable Status = %r\r\n", Status));\r
+ I2cBusFrequencySet(400 * 1000);\r
+\r
+ MmioWrite32(mI2CBaseAddress + R_IC_INTR_MASK, 0x0);\r
+ if (0x7f < SlaveAddress )\r
+ SlaveAddress = ( SlaveAddress & 0x3ff ) | IC_TAR_10BITADDR_MASTER;\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_RX_TL, 0);\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_TX_TL, 0 );\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_CON, mI2cMode);\r
+ Status = I2cEnable();\r
+\r
+ DEBUG((EFI_D_INFO, "I2cEnable Status = %r\r\n", Status));\r
+ MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Reads a Byte from I2C Device.\r
+ \r
+ @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
+ @param SlaveAddress Device Address from which the byte value has to be read\r
+ @param Offset Offset from which the data has to be read\r
+ @param *Byte Address to which the value read has to be stored\r
+ @param Start Whether a RESTART is issued before the byte is sent or received\r
+ @param End Whether STOP is generated after a data byte is sent or received \r
+ \r
+ @return EFI_SUCCESS IF the byte value has been successfully read\r
+ @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
+**/\r
+EFI_STATUS \r
+ByteReadI2CBasic(\r
+ IN UINT8 I2cControllerIndex,\r
+ IN UINT8 SlaveAddress,\r
+ IN UINTN ReadBytes,\r
+ OUT UINT8 *ReadBuffer,\r
+ IN UINT8 Start,\r
+ IN UINT8 End\r
+ )\r
+{\r
+\r
+ EFI_STATUS Status;\r
+ UINT32 I2cStatus;\r
+ UINT16 ReceiveData;\r
+ UINT8 *ReceiveDataEnd;\r
+ UINT8 *ReceiveRequest;\r
+ UINT16 RawIntrStat;\r
+ UINT32 Count=0;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ ReceiveDataEnd = &ReadBuffer [ReadBytes];\r
+ if( ReadBytes ) {\r
+\r
+ ReceiveRequest = ReadBuffer;\r
+ DEBUG((EFI_D_INFO,"Read: ---------------%d bytes to RX\r\n",ReceiveDataEnd - ReceiveRequest));\r
+\r
+ while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd > ReadBuffer)) {\r
+ \r
+ //\r
+ // Check for NACK\r
+ //\r
+ RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_RawIntrStat);\r
+ if ( 0 != ( RawIntrStat & I2C_INTR_TX_ABRT )) {\r
+ MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );\r
+ Status = RETURN_DEVICE_ERROR;\r
+ DEBUG((EFI_D_INFO,"TX ABRT ,%d bytes hasn't been transferred\r\n",ReceiveDataEnd - ReceiveRequest));\r
+ break;\r
+ }\r
+ \r
+ //\r
+ // Determine if another byte was received\r
+ //\r
+ I2cStatus = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_STATUS);\r
+ if (0 != ( I2cStatus & STAT_RFNE )) {\r
+ ReceiveData = (UINT16)MmioRead32 ( mI2CBaseAddress + R_IC_DATA_CMD );\r
+ *ReadBuffer++ = (UINT8)ReceiveData;\r
+ DEBUG((EFI_D_INFO,"MmioRead32 ,1 byte 0x:%x is received\r\n",ReceiveData));\r
+ }\r
+\r
+ if(ReceiveDataEnd == ReceiveRequest) {\r
+ MicroSecondDelay ( FIFO_WRITE_DELAY );\r
+ DEBUG((EFI_D_INFO,"ReceiveDataEnd==ReceiveRequest------------%x\r\n",I2cStatus & STAT_RFNE));\r
+ Count++;\r
+ if(Count<1024) {\r
+ //\r
+ // To avoid sys hung without ul-pmc device on RVP,\r
+ // waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.\r
+ //\r
+ continue;\r
+ } else {\r
+ break;\r
+ }\r
+ }\r
+ \r
+ //\r
+ // Wait until a read request will fit.\r
+ //\r
+ if (0 == (I2cStatus & STAT_TFNF)) {\r
+ DEBUG((EFI_D_INFO,"Wait until a read request will fit\r\n"));\r
+ MicroSecondDelay (10);\r
+ continue;\r
+ }\r
+ \r
+ //\r
+ // Issue the next read request.\r
+ //\r
+ if(End && Start) {\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART|B_CMD_STOP);\r
+ } else if (!End && Start) {\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART);\r
+ } else if (End && !Start) {\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_STOP);\r
+ } else if (!End && !Start) {\r
+ MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD);\r
+ }\r
+ MicroSecondDelay (FIFO_WRITE_DELAY);\r
+\r
+ ReceiveRequest += 1;\r
+ }\r
+ }\r
+ \r
+ return Status;\r
+}\r
+\r
+/**\r
+ Writes a Byte to I2C Device.\r
+ \r
+ @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
+ @param SlaveAddress Device Address from which the byte value has to be written\r
+ @param Offset Offset from which the data has to be read\r
+ @param *Byte Address to which the value written is stored\r
+ @param Start Whether a RESTART is issued before the byte is sent or received\r
+ @param End Whether STOP is generated after a data byte is sent or received \r
+ \r
+ @return EFI_SUCCESS IF the byte value has been successfully written\r
+ @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
+**/\r
+EFI_STATUS ByteWriteI2CBasic(\r
+ IN UINT8 I2cControllerIndex,\r
+ IN UINT8 SlaveAddress,\r
+ IN UINTN WriteBytes,\r
+ IN UINT8 *WriteBuffer,\r
+ IN UINT8 Start,\r
+ IN UINT8 End\r
+ )\r
+{\r
+\r
+ EFI_STATUS Status;\r
+ UINT32 I2cStatus;\r
+ UINT8 *TransmitEnd;\r
+ UINT16 RawIntrStat;\r
+ UINT32 Count=0;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ Status=I2CInit(I2cControllerIndex, SlaveAddress);\r
+ if(Status!=EFI_SUCCESS)\r
+ return Status;\r
+\r
+ TransmitEnd = &WriteBuffer[WriteBytes];\r
+ if( WriteBytes ) {\r
+ DEBUG((EFI_D_INFO,"Write: --------------%d bytes to TX\r\n",TransmitEnd - WriteBuffer));\r
+ while (TransmitEnd > WriteBuffer) {\r
+ I2cStatus = MmioRead32 (mI2CBaseAddress + R_IC_STATUS);\r
+ RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_RawIntrStat);\r
+ if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {\r
+ MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT);\r
+ Status = RETURN_DEVICE_ERROR;\r
+ DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));\r
+ break;\r
+ }\r
+ if (0 == (I2cStatus & STAT_TFNF)) {\r
+ //\r
+ // If TX not full , will send cmd or continue to wait\r
+ //\r
+ MicroSecondDelay (FIFO_WRITE_DELAY);\r
+ continue;\r
+ }\r
+\r
+ if(End && Start) {\r
+ MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_RESTART|B_CMD_STOP);\r
+ } else if (!End && Start) {\r
+ MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_RESTART);\r
+ } else if (End && !Start) {\r
+ MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_STOP);\r
+ } else if (!End && !Start ) {\r
+ MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++));\r
+ }\r
+ \r
+ //\r
+ // Add a small delay to work around some odd behavior being seen. Without this delay bytes get dropped.\r
+ //\r
+ MicroSecondDelay ( FIFO_WRITE_DELAY );//wait after send cmd\r
+ \r
+ //\r
+ // Time out\r
+ //\r
+ while(1) {\r
+ RawIntrStat = MmioRead16 ( mI2CBaseAddress + R_IC_RawIntrStat );\r
+ if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {\r
+ MmioRead16 (mI2CBaseAddress + R_IC_CLR_TX_ABRT);\r
+ Status = RETURN_DEVICE_ERROR;\r
+ DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));\r
+ }\r
+ if(0 == MmioRead16(mI2CBaseAddress + R_IC_TXFLR)) break;\r
+\r
+ MicroSecondDelay (FIFO_WRITE_DELAY);\r
+ Count++;\r
+ if(Count<1024) {\r
+ //\r
+ // to avoid sys hung without ul-pmc device on RVP.\r
+ // Waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.\r
+ //\r
+ continue;\r
+ } else {\r
+ break;\r
+ }\r
+ }//while( 1 )\r
+ }\r
+\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Reads a Byte from I2C Device.\r
+ \r
+ @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
+ @param SlaveAddress Device Address from which the byte value has to be read\r
+ @param Offset Offset from which the data has to be read\r
+ @param ReadBytes Number of bytes to be read\r
+ @param *ReadBuffer Address to which the value read has to be stored\r
+ \r
+ @return EFI_SUCCESS IF the byte value has been successfully read\r
+ @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
+**/\r
+EFI_STATUS ByteReadI2C(\r
+ IN UINT8 I2cControllerIndex,\r
+ IN UINT8 SlaveAddress,\r
+ IN UINT8 Offset,\r
+ IN UINTN ReadBytes,\r
+ OUT UINT8 *ReadBuffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((EFI_D_INFO, "ByteReadI2C:---offset:0x%x\n",Offset));\r
+ Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,1,&Offset,TRUE,FALSE);\r
+ Status = ByteReadI2CBasic(I2cControllerIndex, SlaveAddress,ReadBytes,ReadBuffer,TRUE,TRUE);\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Writes a Byte to I2C Device.\r
+ \r
+ @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r
+ @param SlaveAddress Device Address from which the byte value has to be written\r
+ @param Offset Offset from which the data has to be written\r
+ @param WriteBytes Number of bytes to be written\r
+ @param *Byte Address to which the value written is stored\r
+ \r
+ @return EFI_SUCCESS IF the byte value has been successfully read\r
+ @return EFI_DEVICE_ERROR Operation Failed, Device Error\r
+**/\r
+EFI_STATUS ByteWriteI2C(\r
+ IN UINT8 I2cControllerIndex,\r
+ IN UINT8 SlaveAddress,\r
+ IN UINT8 Offset,\r
+ IN UINTN WriteBytes,\r
+ IN UINT8 *WriteBuffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((EFI_D_INFO, "ByteWriteI2C:---offset/bytes/buf:0x%x,0x%x,0x%x,0x%x\n",Offset,WriteBytes,WriteBuffer,*WriteBuffer));\r
+ Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,1,&Offset,TRUE,FALSE);\r
+ Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,WriteBytes,WriteBuffer,FALSE,TRUE);\r
+\r
+ return Status;\r
+}\r