The ARM Architecture Reference Manual for ARMv8-A defines up to
seven levels of cache, L1 through L7.
Define MAX_ARM_CACHE_LEVEL to be 7.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
+// The ARM Architecture Reference Manual for ARMv8-A defines up\r
+// to 7 levels of cache, L1 through L7.\r
+#define MAX_ARM_CACHE_LEVEL 7\r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r