REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2018
Current FSP SEC_IDT_TABLE structure is not natural aligned:
typedef struct _SEC_IDT_TABLE {
EFI_PEI_SERVICES *PeiService;
UINT64 IdtTable[];
} SEC_IDT_TABLE;
Compiler will insert DWORD padding between 2 elements and
GetPeiServicesTablePointer() in early phase then always
returns padding data from stack, which was not reset to 0
in SecMain.
Solution is to align FSP SEC_IDT_TABLE structure to UefiCpuPkg
to have UINT64 as PeiService field and reset it to 0.
Test: Verified on internal platform and booting successfully
with FSP API mode.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
// | |\r
// | |\r
// |-------------------|----> TempRamBase\r
- IdtTableInStack.PeiService = NULL;\r
+ IdtTableInStack.PeiService = 0;\r
AsmReadIdtr (&IdtDescriptor);\r
if (IdtDescriptor.Base == 0) {\r
ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);\r
/** @file\r
\r
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
);\r
\r
typedef struct _SEC_IDT_TABLE {\r
- EFI_PEI_SERVICES *PeiService;\r
+ //\r
+ // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base\r
+ // address should be 8-byte alignment.\r
+ // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
+ // EFI_PEI_SERVICES**\r
+ //\r
+ UINT64 PeiService;\r
UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];\r
} SEC_IDT_TABLE;\r
\r