MdePkg: Add ASSERT to handle local APIC not config properly

When the local APIC is not configurated properly, function
InternalX86GetInitTimerCount() may return zero, which will lead to a
divide by zero exception in SecPeiDxeTimerLibCpu.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18593 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c b/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
index 7b2bc54934ef523f65142f62d53eb626d568cd5d..76c66fbce6fb9f1e710185fbe5e899903ef42f1e 100644 (file)
--- a/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
+++ b/MdePkg/Library/SecPeiDxeTimerLibCpu/X86TimerLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   Timer Library functions built upon local APIC on IA32/x64.\r
 \r
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -19,6 +19,7 @@
 #include <Library/PcdLib.h>\r
 #include <Library/DebugLib.h>\r
 \r
+#define APIC_SVR        0x0f0\r
 #define APIC_LVTERR     0x370\r
 #define APIC_TMICT      0x380\r
 #define APIC_TMCCT      0x390\r
@@ -39,6 +40,11 @@ CONST UINT8                           mTimerLibLocalApicDivisor[] = {
 /**\r
   Internal function to retrieve the base address of local APIC.\r
 \r
+  This function will ASSERT if:\r
+  The local APIC is not globally enabled.\r
+  The local APIC is not working under XAPIC mode.\r
+  The local APIC is not software enabled.\r
+\r
   @return The base address of local APIC\r
 \r
 **/\r
@@ -48,7 +54,32 @@ InternalX86GetApicBase (
   VOID\r
   )\r
 {\r
-  return (UINTN)AsmMsrBitFieldRead64 (27, 12, 35) << 12;\r
+  UINTN                             MsrValue;\r
+  UINTN                             ApicBase;\r
+\r
+  MsrValue = (UINTN) AsmReadMsr64 (27);\r
+  ApicBase = MsrValue & 0xffffff000ULL;\r
+\r
+  //\r
+  // Check the APIC Global Enable bit (bit 11) in IA32_APIC_BASE MSR.\r
+  // This bit will be 1, if local APIC is globally enabled.\r
+  //\r
+  ASSERT ((MsrValue & BIT11) != 0);\r
+\r
+  //\r
+  // Check the APIC Extended Mode bit (bit 10) in IA32_APIC_BASE MSR.\r
+  // This bit will be 0, if local APIC is under XAPIC mode.\r
+  //\r
+  ASSERT ((MsrValue & BIT10) == 0);\r
+\r
+  //\r
+  // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
+  // Vector Register.\r
+  // This bit will be 1, if local APIC is software enabled.\r
+  //\r
+  ASSERT ((MmioRead32 (ApicBase + APIC_SVR) & BIT8) != 0);\r
+\r
+  return ApicBase;\r
 }\r
 \r
 /**\r
@@ -109,6 +140,9 @@ InternalX86GetInitTimerCount (
   Stalls the CPU for at least the given number of ticks. It's invoked by\r
   MicroSecondDelay() and NanoSecondDelay().\r
 \r
+  This function will ASSERT if the APIC timer intial count returned from\r
+  InternalX86GetInitTimerCount() is zero.\r
+\r
   @param  ApicBase  The base address of memory mapped registers of local APIC.\r
   @param  Delay     A period of time to delay in ticks.\r
 \r
@@ -133,6 +167,7 @@ InternalX86Delay (
   // Delay and the Init Count.\r
   //\r
   InitCount = InternalX86GetInitTimerCount (ApicBase);\r
+  ASSERT (InitCount != 0);\r
   Times     = Delay / (InitCount / 2);\r
   Delay     = Delay % (InitCount / 2);\r
 \r