/** @file\r
- The definition for iSCSI Boot Firmware Table, it's defined in\r
- Microsoft iBFT document. \r
+ The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's\r
+ iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification. \r
\r
Copyright (c) 2006 - 2008, Intel Corporation\r
All rights reserved. This program and the accompanying materials \r
IpPrefixOriginUnchanged = 16\r
} IP_PREFIX_VALUE;\r
\r
-#pragma pack(1)\r
-\r
///\r
/// iBF Table Header\r
///\r
UINT16 Target1Offset; \r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER 0x1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0\r
\r
///\r
/// Initiator Structure\r
UINT16 IScsiNameOffset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID 0x1 \r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED 0x2 \r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0 \r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1 \r
\r
///\r
/// NIC Structure\r
UINT16 HostNameOffset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID 0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED 0x2\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL 0x4\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1\r
+\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2\r
\r
///\r
/// Target Structure\r
UINT16 ReverseCHAPSecretOffset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID 0x1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED 0x2\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP 0x4\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP 0x8\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1\r
\r
-#pragma pack()\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3\r
\r
#endif\r
\r
\r
#define MBR_SIZE 512\r
\r
-#pragma pack(1)\r
-//\r
-// MBR Partition Entry\r
-//\r
+///\r
+/// MBR Partition Entry\r
+///\r
typedef struct {\r
UINT8 BootIndicator;\r
UINT8 StartHead;\r
UINT16 Signature;\r
} MASTER_BOOT_RECORD;\r
\r
-#pragma pack()\r
-\r
#endif\r
#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_\r
#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack(1)\r
-\r
///\r
/// Memory Mapped Configuration Space Access Table (MCFG)\r
/// This table is a basic description table header followed by\r
///\r
#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01\r
\r
-#pragma pack()\r
-\r
#endif\r
#define PCI_MAX_FUNC 7\r
\r
\r
-#pragma pack(1)\r
typedef struct {\r
UINT16 VendorId;\r
UINT16 DeviceId;\r
UINT16 BridgeControl; ///< Bridge Control\r
} PCI_CARDBUS_CONTROL_REGISTER;\r
\r
-///\r
-/// Definitions of PCI class bytes and manipulation macros.\r
-///\r
+//\r
+// Definitions of PCI class bytes and manipulation macros.\r
+//\r
#define PCI_CLASS_OLD 0x00\r
#define PCI_CLASS_OLD_OTHER 0x00\r
#define PCI_CLASS_OLD_VGA 0x01\r
#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
\r
-///\r
-/// defined in PCI-to-PCI Bridge Architecture Specification\r
-///\r
+//\r
+// defined in PCI-to-PCI Bridge Architecture Specification\r
+//\r
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
UINT32 Uint32;\r
} PCI_CONFIG_ACCESS_CF8;\r
\r
-#pragma pack()\r
-\r
#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
\r
-///\r
-/// defined in PCI-to-PCI Bridge Architecture Specification\r
-///\r
+//\r
+// defined in PCI-to-PCI Bridge Architecture Specification\r
+//\r
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r
#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r
#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r
\r
-///\r
-/// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
-///\r
+//\r
+// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
+//\r
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
///\r
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
\r
-#pragma pack(1)\r
//\r
// PCI Capability List IDs and records\r
//\r
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+\r
typedef struct {\r
UINT8 CapabilityID;\r
UINT8 NextItemPtr;\r
EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
} EFI_PCI_ROM_HEADER;\r
\r
-#pragma pack()\r
-\r
#endif\r
//\r
#define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r
\r
-#pragma pack(1)\r
///\r
/// Capability EFI_PCI_CAPABILITY_ID_PCIX, defined in PCI-X Addendum to the PCI Local Bus Specification\r
///\r
UINT32 SplitTransCtrlRegDn;\r
} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
\r
-#pragma pack()\r
-\r
#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
\r
#endif\r
///\r
#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r
\r
-#pragma pack(1)\r
-\r
///\r
/// defined in PCI Firmware Specification\r
///\r
UINT16 DMTFCLPEntryPointOffset;\r
} PCI_3_0_DATA_STRUCTURE;\r
\r
-#pragma pack()\r
-\r
#endif\r
///\r
/// SAL System Table Definitions\r
///\r
-#pragma pack(1)\r
typedef struct {\r
///\r
/// The ASCII string representation of "SST_" which confirms the presence of the table. \r
///\r
UINT8 Reserved2[8];\r
} SAL_SYSTEM_TABLE_HEADER;\r
-#pragma pack()\r
\r
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
#define EFI_SAL_REVISION 0x0320\r
#define EFI_SAL_ST_PTC_SIZE 16\r
#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
\r
-#pragma pack(1)\r
///\r
/// Format Entrypoint Descriptor Entry\r
///\r
UINT64 Reserved2[2];\r
} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
\r
-#pragma pack(1)\r
///\r
/// Format Platform Features Descriptor Entry\r
///\r
UINT8 PlatformFeatures;\r
UINT8 Reserved[14];\r
} SAL_ST_PLATFORM_FEATURES;\r
-#pragma pack()\r
+\r
//\r
// Value of Platform Feature List\r
//\r
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
\r
-#pragma pack(1)\r
///\r
/// Format of Translation Register Descriptor Entry\r
///\r
UINT64 EncodedPageSize;\r
UINT64 Reserved1;\r
} SAL_ST_TR_DECRIPTOR;\r
-#pragma pack()\r
+\r
//\r
// Type of Translation Register\r
//\r
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
#define EFI_SAL_ST_TR_USAGE_DATA 01\r
\r
-#pragma pack(1)\r
///\r
/// Definition of Coherence Domain Information\r
///\r
UINT64 NumberOfProcessors;\r
UINT64 LocalIDRegister;\r
} SAL_COHERENCE_DOMAIN_INFO;\r
-#pragma pack()\r
\r
-#pragma pack(1)\r
///\r
/// Format of Purge Translation Cache Coherence Domain Entry\r
///\r
UINT32 NumberOfDomains;\r
SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
-#pragma pack()\r
\r
-#pragma pack(1)\r
///\r
/// Format of Application Processor Wake-Up Descriptor Entry\r
///\r
UINT8 Reserved[6];\r
UINT64 ExternalInterruptVector;\r
} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
-#pragma pack()\r
\r
///\r
/// Format of Firmware Interface Table (FIT) Entry\r
#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
+\r
+#pragma pack(1)\r
+\r
///\r
/// Definition of Processor Machine Check Error Record\r
///\r
PSI_STATIC_STRUCT PsiValidData;\r
} SAL_PROCESSOR_ERROR_RECORD;\r
\r
+#pragma pack()\r
+\r
///\r
/// GUID of Platform Memory Device Error Info\r
///\r
UINT8 SegmentNumber;\r
UINT8 Reserved[5];\r
} PCI_COMP_INFO;\r
+\r
///\r
/// Definition of Platform PCI Component Error Info\r
///\r
#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
+\r
+#pragma pack(1)\r
///\r
/// Definition of Platform SEL Device Error Info Record\r
///\r
UINT8 Data2;\r
UINT8 Data3;\r
} SAL_SEL_DEVICE_ERROR_RECORD;\r
+#pragma pack()\r
\r
///\r
/// GUID of Platform SMBIOS Device Error Info\r
UINT8 *Raw;\r
} SAL_ERROR_RECORDS_POINTERS;\r
\r
-#pragma pack()\r
-\r
#endif\r
//\r
#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type\r
\r
-#pragma pack(1)\r
///\r
/// Standard INQUIRY data format\r
///\r
UINT8 BlockSize0;\r
} EFI_SCSI_DISK_CAPACITY_DATA;\r
\r
-#pragma pack()\r
-\r
//\r
// Sense Key\r
//\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack(1)\r
-\r
///\r
/// SPCR Revision (defined in spec)\r
///\r
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x01\r
\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
///\r
/// Serial Port Console Redirection Table Format\r
///\r
UINT8 PciSegment;\r
UINT32 Reserved2;\r
} EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE;\r
-\r
#pragma pack()\r
\r
//\r
///\r
/// Smbios Table Entry Point Structure\r
///\r
-#pragma pack(1)\r
typedef struct {\r
UINT8 AnchorString[4];\r
UINT8 EntryPointStructureChecksum;\r
\r
typedef UINT8 SMBIOS_TABLE_STRING;\r
\r
+#pragma pack(1)\r
///\r
/// BIOS Information (Type 0)\r
///\r
UINT8 EmbeddedControllerFirmwareMajorRelease;\r
UINT8 EmbeddedControllerFirmwareMinorRelease;\r
} SMBIOS_TABLE_TYPE0;\r
+#pragma pack()\r
\r
///\r
/// System Information (Type 1)\r
SMBIOS_TABLE_STRING Family;\r
} SMBIOS_TABLE_TYPE1;\r
\r
+#pragma pack(1)\r
///\r
/// Base Board (or Module) Information (Type 2)\r
///\r
UINT8 NumberOfContainedObjectHandles;\r
UINT16 ContainedObjectHandles[1];\r
} SMBIOS_TABLE_TYPE2;\r
+#pragma pack()\r
\r
typedef struct {\r
UINT8 ContainedElementType;\r
UINT16 ProcessorFamily2;\r
} SMBIOS_TABLE_TYPE4;\r
\r
+#pragma pack(1)\r
///\r
/// Memory Controller Information (Type 5, Obsolete)\r
///\r
UINT8 SystemCacheType;\r
UINT8 Associativity;\r
} SMBIOS_TABLE_TYPE7;\r
+#pragma pack()\r
\r
///\r
/// Port Connector Information (Type 8)\r
UINT8 PortType;\r
} SMBIOS_TABLE_TYPE8;\r
\r
+#pragma pack(1)\r
///\r
/// System Slots (Type 9)\r
///\r
UINT8 BusNum;\r
UINT8 DevFuncNum;\r
} SMBIOS_TABLE_TYPE9;\r
+#pragma pack()\r
\r
typedef struct {\r
UINT8 DeviceType;\r
SMBIOS_TABLE_STRING CurrentLanguages;\r
} SMBIOS_TABLE_TYPE13;\r
\r
+#pragma pack(1)\r
typedef struct {\r
UINT8 ItemType;\r
UINT16 ItemHandle;\r
UINT32 DeviceErrorAddress;\r
UINT32 ErrorResolution;\r
} SMBIOS_TABLE_TYPE18;\r
+#pragma pack()\r
\r
///\r
/// Memory Array Mapped Address (Type 19)\r
UINT8 NumberOfButtons;\r
} SMBIOS_TABLE_TYPE21;\r
\r
+#pragma pack(1)\r
///\r
/// Portable Battery (Type 22)\r
///\r
UINT16 TimerInterval;\r
UINT16 Timeout;\r
} SMBIOS_TABLE_TYPE23;\r
+#pragma pack()\r
\r
///\r
/// Hardware Security (Type 24)\r
UINT8 BootStatus[1];\r
} SMBIOS_TABLE_TYPE32;\r
\r
+#pragma pack(1)\r
///\r
/// 64-bit Memory Error Information (Type 33)\r
///\r
UINT16 ComponentHandle;\r
UINT16 ThresholdHandle;\r
} SMBIOS_TABLE_TYPE35;\r
+#pragma pack()\r
\r
///\r
/// Management Device Threshold Data (Type 36)\r
UINT16 UpperThresholdNonRecoverable;\r
} SMBIOS_TABLE_TYPE36;\r
\r
+#pragma pack(1)\r
typedef struct {\r
UINT8 DeviceLoad;\r
UINT16 DeviceHandle;\r
UINT8 MemoryDeviceCount;\r
MEMORY_DEVICE MemoryDevice[1];\r
} SMBIOS_TABLE_TYPE37;\r
+#pragma pack()\r
\r
///\r
/// IPMI Device Information (Type 38)\r
UINT16 InputCurrentProbeHandle;\r
} SMBIOS_TABLE_TYPE39;\r
\r
+#pragma pack(1)\r
typedef struct { \r
UINT8 EntryLength; \r
UINT16 ReferencedHandle;\r
UINT8 BusNum;\r
UINT8 DevFuncNum; \r
} SMBIOS_TABLE_TYPE41;\r
+#pragma pack()\r
\r
///\r
/// Inactive (Type 126)\r
UINT8 *Raw;\r
} SMBIOS_STRUCTURE_POINTER;\r
\r
-#pragma pack()\r
-\r
#endif\r
//\r
// Structures are all packed on 1-byte alignment\r
//\r
-\r
#pragma pack (1)\r
\r
//\r
//\r
// USB standard descriptors and reqeust\r
//\r
-#pragma pack(1)\r
\r
///\r
/// Format of Setup Data for USB Device Requests\r
CHAR16 String[1];\r
} EFI_USB_STRING_DESCRIPTOR;\r
\r
-#pragma pack()\r
-\r
-\r
typedef enum {\r
//\r
// USB request type\r
UINT8 DescriptorType;\r
UINT16 DescriptorLength;\r
} EFI_USB_HID_CLASS_DESCRIPTOR;\r
+#pragma pack()\r
\r
///\r
/// The HID descriptor identifies the length and type\r
EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1];\r
} EFI_USB_HID_DESCRIPTOR;\r
\r
-#pragma pack()\r
-\r
#endif\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack(1)\r
///\r
/// Watchdog Action Table definition.\r
///\r
UINT32 Mask;\r
} EFI_ACPI_WATCHDOG_ACTION_1_0_WATCHDOG_ACTION_INSTRUCTION_ENTRY;\r
\r
-#pragma pack()\r
-\r
///\r
/// WDAT Revision (defined in spec)\r
///\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack(1)\r
-\r
///\r
/// Watchdog Resource Table definition.\r
///\r
UINT8 Units;\r
} EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE;\r
\r
-#pragma pack()\r
-\r
//\r
// WDRT Revision (defined in spec)\r
//\r