This new PCD is used to specify the AP loop mode during POST phase.
The value 1 means we will place AP in the Hlt-Loop state by HLT instruction.
BSP need to send INIT-SIPI-SIPI to wake up APs.
The value 2 means we will place AP in the deepest C-state by MWAIT instruction.
BSP need to modify the monitor buffer by MONITOR instruction to wake up APs.
The value 3 means we will place AP in the Run-loop state. APs are running.
BSP need to write one semaphore to wake up APs.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19341
6f19259b-4bc3-4df7-8a09-
765794883524
## Specifies the size of the microcode Region.\r
# @Prompt Microcode Region size.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
+ ## Specifies the AP wait loop state during POST phase.\r
+ # The value is defined as below.<BR><BR>\r
+ # 1: Place AP in the Hlt-Loop state.<BR>\r
+ # 2: Place AP in the Mwait-Loop state.<BR>\r
+ # 3: Place AP in the Run-Loop state.<BR>\r
+ # @Prompt The AP wait loop state.\r
+ # @ValidRange 0x80000001 | 1 - 3\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuNumberOfReservedVariableMtrrs_HELP #language en-US "Specifies the number of variable MTRRs reserved for OS use."\r
\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApLoopMode_PROMPT #language en-US "The AP wait loop state"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApLoopMode_HELP #language en-US "Specifies the AP wait loop state during POST phase."\r
+\r