--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; CpuFlushTlb() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT CpuFlushTlb\r
+ AREA BaseCpuLib_LowLevel, CODE, READONLY\r
+\r
+;/**\r
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+;\r
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;CpuFlushTlb (\r
+; VOID\r
+; );\r
+;\r
+CpuFlushTlb\r
+ tlbi vmalle1 // Invalidate Inst TLB and Data TLB\r
+ dsb sy\r
+ isb\r
+ ret\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; CpuSleep() for AArch64\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+; Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT CpuSleep\r
+ AREA BaseCpuLib_LowLevel, CODE, READONLY\r
+\r
+;/**\r
+; Places the CPU in a sleep state until an interrupt is received.\r
+;\r
+; Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+; are disabled prior to calling this function, then the CPU will be placed in a\r
+; sleep state indefinitely.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;CpuSleep (\r
+; VOID\r
+; );\r
+;\r
+\r
+CpuSleep\r
+ wfi\r
+ ret\r
+\r
+ END\r
## @file\r
# Instance of CPU Library for various architecture.\r
#\r
-# CPU Library implemented using ASM functions for IA-32 and X64,\r
+# CPU Library implemented using ASM functions for IA32, X64, ARM, AARCH64,\r
# PAL CALLs for IPF, and empty functions for EBC.\r
#\r
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
Arm/CpuSleep.S | GCC \r
\r
[Sources.AARCH64]\r
- AArch64/CpuFlushTlb.S | GCC\r
- AArch64/CpuSleep.S | GCC\r
+ AArch64/CpuFlushTlb.S | GCC\r
+ AArch64/CpuSleep.S | GCC\r
+ AArch64/CpuFlushTlb.asm | MSFT\r
+ AArch64/CpuSleep.asm | MSFT\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r