No platform uses this so remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
+++ /dev/null
-#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-#include <Drivers/PL35xSmc.h>\r
-\r
-.text\r
-\r
-#Maintain 8 byte alignment\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(PL35xSmcInitialize)\r
-GCC_ASM_EXPORT(PL35xSmcSetRefresh)\r
-\r
-// IN r1 Smc Base Address\r
-// IN r2 Smc Configuration Start Address\r
-// IN r3 Smc Configuration End Address\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-ASM_PFX(PL35xSmcInitialize):\r
- // While (SmcConfigurationStart < SmcConfigurationEnd)\r
- cmp r2, r3\r
- blxge lr\r
-\r
- // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- ldr r0, [r2, #0x4]\r
- str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
-\r
- // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- ldr r0, [r2, #0x8]\r
- str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
-\r
- // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
- ldr r4, [r2, #0x0]\r
- orr r0, r0, r4\r
- str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
-\r
- add r2, #0xC\r
- b ASM_PFX(PL35xSmcInitialize)\r
-\r
-// IN r1 Smc Base Address\r
-// IN r2 Smc Refresh Period 0\r
-// IN r3 Smc Refresh Period 1\r
-ASM_PFX(PL35xSmcSetRefresh):\r
- str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]\r
- str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]\r
- blx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Drivers/PL35xSmc.h>\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT PL35xSmcInitialize\r
- EXPORT PL35xSmcSetRefresh\r
-\r
- PRESERVE8\r
- AREA ModuleInitializeSMC, CODE, READONLY\r
-\r
-// IN r1 Smc Base Address\r
-// IN r2 Smc Configuration Start Address\r
-// IN r3 Smc Configuration End Address\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-PL35xSmcInitialize\r
- // While (SmcConfigurationStart < SmcConfigurationEnd)\r
- cmp r2, r3\r
- blxge lr\r
-\r
- // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- ldr r0, [r2, #0x4]\r
- str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
-\r
- // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- ldr r0, [r2, #0x8]\r
- str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
-\r
- // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
- ldr r4, [r2, #0x0]\r
- orr r0, r0, r4\r
- str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
-\r
- add r2, #0xC\r
- b PL35xSmcInitialize\r
-\r
-// IN r1 Smc Base Address\r
-// IN r2 Smc Refresh Period 0\r
-// IN r3 Smc Refresh Period 1\r
-PL35xSmcSetRefresh\r
- str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]\r
- str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]\r
- blx lr\r
-\r
- END\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL35xSmc\r
- FILE_GUID = 10952220-aa32-11df-a438-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PL35xSmcLib\r
-\r
-[Sources.common]\r
- InitializeSMC.asm | RVCT\r
- InitializeSMC.S | GCC\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- MdePkg/MdePkg.dec\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef PL35xSMC_H_\r
-#define PL35xSMC_H_\r
-\r
-#define PL350_SMC_DIRECT_CMD_OFFSET 0x10\r
-#define PL350_SMC_SET_CYCLES_OFFSET 0x14\r
-#define PL350_SMC_SET_OPMODE_OFFSET 0x18\r
-#define PL350_SMC_REFRESH_0_OFFSET 0x20\r
-#define PL350_SMC_REFRESH_1_OFFSET 0x24\r
-\r
-#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)\r
-#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)\r
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)\r
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)\r
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)\r
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)\r
-#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))\r
-#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)\r
-\r
-#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)\r
-#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)\r
-#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)\r
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)\r
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)\r
-#define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)\r
-#define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)\r
-#define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)\r
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)\r
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)\r
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)\r
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)\r
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)\r
-\r
-#define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)\r
-#define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)\r
-#define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)\r
-#define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)\r
-#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)\r
-#define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)\r
-#define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)\r
-\r
-#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)\r
-#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)\r
-#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)\r
-#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)\r
-#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)\r
-#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)\r
-#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)\r
-\r
-#endif\r
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