1. Add address check for "RegisterForRuntime" APIs of PciLib, PciCf8Lib, PciExpressLi...

2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class.

3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/Library/PciCf8Lib.h b/MdePkg/Include/Library/PciCf8Lib.h
index f508aa6dfac5bf623e4f1e3890a41a0ed692ca25..080889d9e26759e10369deb8d6457605efd0680c 100644 (file)
--- a/MdePkg/Include/Library/PciCf8Lib.h
+++ b/MdePkg/Include/Library/PciCf8Lib.h
@@ -5,7 +5,7 @@
   configuration cycles must be though I/O ports 0xCF8 and 0xCFC.  This library only allows \r
   access to PCI Segment #0.\r
 \r
-Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
 All rights reserved. This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -47,6 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
   \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If the register specified by Address >= 0x100, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r

diff --git a/MdePkg/Include/Library/PciSegmentLib.h b/MdePkg/Include/Library/PciSegmentLib.h
index 9eaab0c2e77ef45dfb7f9f4dc4210a92f15467a4..ef1e3ac4511d74b6b7ff8f50da2d15f6a62270a9 100644 (file)
--- a/MdePkg/Include/Library/PciSegmentLib.h
+++ b/MdePkg/Include/Library/PciSegmentLib.h
@@ -23,7 +23,7 @@
   access method.  Modules will typically use the PCI Segment Library for its PCI configuration \r
   accesses when PCI Segments other than Segment #0 must be accessed.  \r
 \r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
 All rights reserved. This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -67,7 +67,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Register a PCI device so PCI configuration registers may be accessed after \r
   SetVirtualAddressMap().\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -112,7 +112,7 @@ PciSegmentRead8 (
   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
   @param  Value       The value to write.\r
@@ -969,7 +969,7 @@ PciSegmentBitFieldAndThenOr32 (
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
@@ -1001,7 +1001,7 @@ PciSegmentReadBuffer (
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r

diff --git a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
index a9af173783042db65862eeed7947d0d28f7e06b7..f0a23c3605ebe58e49f781bc08680c27c53d93b5 100644 (file)
--- a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
+++ b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
@@ -2,7 +2,7 @@
   PCI CF8 Library functions that use I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
   Layers on top of an I/O Library instance.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -68,6 +68,7 @@
   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
   \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If the register specified by Address >= 0x100, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -87,6 +88,7 @@ PciCf8RegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
   return RETURN_SUCCESS;\r
 }\r
 \r

diff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
index f74410a565bd9574e3cc373578211165cdca6354..2220c9a4f94a855011eb769e0d6ef0233b849415 100644 (file)
--- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
+++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
@@ -5,7 +5,7 @@
   All assertions for I/O operations are handled in MMIO functions in the IoLib\r
   Library.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -64,6 +64,7 @@ PciExpressRegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_ADDRESS (Address);\r
   return RETURN_UNSUPPORTED;\r
 }\r
 \r

diff --git a/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c b/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
index 1406813f43e0f078bacd0518f7bc2eb389fc17ff..01306b7b926a1856f9395a2397e5808c0de12c55 100644 (file)
--- a/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
+++ b/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI Library using PCI CFG2 PPI.\r
 \r
-  Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+  Copyright (c) 2007 - 2009, Intel Corporation All rights\r
   reserved. This program and the accompanying materials are\r
   licensed and made available under the terms and conditions of\r
   the BSD License which accompanies this distribution.  The full\r
@@ -155,6 +155,7 @@ PciRegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
   return RETURN_UNSUPPORTED;\r
 }\r
 \r

diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 6c327e2eb9164ff295888c9d7363cd0161e438f9..332d2a9b45e7eb3d6eabf034806f5d6005e3cc58 100644 (file)
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI Segment Library implementation using PCI CFG2 PPI.\r
 \r
-  Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+  Copyright (c) 2007 - 2009, Intel Corporation All rights\r
   reserved. This program and the accompanying materials are\r
   licensed and made available under the terms and conditions of\r
   the BSD License which accompanies this distribution.  The full\r
@@ -25,14 +25,14 @@
 \r
 /**\r
   Assert the validity of a PCI Segment address.\r
-  A valid PCI Segment address should not contain 1's in bits 31:28\r
+  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r
 \r
   @param  A The address to validate.\r
   @param  M Additional bits to assert to be zero.\r
 \r
 **/\r
 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
-  ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
+  ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
 \r
 /**\r
   Translate PCI Lib address into format of PCI CFG2 PPI.\r
@@ -165,7 +165,7 @@ PeiPciSegmentLibPciCfg2WriteWorker (
   Register a PCI device so PCI configuration registers may be accessed after \r
   SetVirtualAddressMap().\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -185,6 +185,7 @@ PciSegmentRegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
   return RETURN_UNSUPPORTED;\r
 }\r
 \r
@@ -218,7 +219,7 @@ PciSegmentRead8 (
   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
   @param  Value       The value to write.\r
@@ -1208,7 +1209,7 @@ PciSegmentBitFieldAndThenOr32 (
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
@@ -1307,7 +1308,7 @@ PciSegmentReadBuffer (
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r

diff --git a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
index ff95ec7862a49119b2dcaf46357ac53fef281fac..1f236753649b09d0b64165f32802ee3472a1d144 100644 (file)
--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI Library using PCI Root Bridge I/O Protocol.\r
 \r
-  Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+  Copyright (c) 2007 - 2009, Intel Corporation All rights\r
   reserved. This program and the accompanying materials are\r
   licensed and made available under the terms and conditions of\r
   the BSD License which accompanies this distribution.  The full\r
@@ -169,6 +169,7 @@ PciRegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
   return RETURN_UNSUPPORTED;\r
 }\r
 \r

diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
index beb8b64adfd11146c80a970d099073907395ba68..97fd240a0e8658042f8bfad416e72d64785d5d97 100644 (file)
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI Segment Library implementation using PCI Root Bridge I/O Protocol.\r
 \r
-  Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+  Copyright (c) 2007 - 2009, Intel Corporation All rights\r
   reserved. This program and the accompanying materials are\r
   licensed and made available under the terms and conditions of\r
   the BSD License which accompanies this distribution.  The full\r
@@ -244,7 +244,7 @@ DxePciSegmentLibPciRootBridgeIoWriteWorker (
   Register a PCI device so PCI configuration registers may be accessed after \r
   SetVirtualAddressMap().\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -264,6 +264,7 @@ PciSegmentRegisterForRuntimeAccess (
   IN UINTN  Address\r
   )\r
 {\r
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
   return RETURN_UNSUPPORTED;\r
 }\r
 \r
@@ -297,7 +298,7 @@ PciSegmentRead8 (
   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
   \r
-  If Address > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
   @param  Value       The value to write.\r
@@ -1287,7 +1288,7 @@ PciSegmentBitFieldAndThenOr32 (
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
@@ -1385,7 +1386,7 @@ PciSegmentReadBuffer (
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
-  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+  If any reserved bits in StartAddress are set, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r

diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h
index ea9fe6665e63331502bae3af0126737d2791d9ef..2633b6d3c5304bfc9d65db0d74c2cc9e5167c43e 100644 (file)
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h
@@ -1,7 +1,7 @@
 /** @file\r
   Include file of PciSegmentPciRootBridgeIo Library.\r
 \r
-  Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+  Copyright (c) 2007 - 2009, Intel Corporation All rights\r
   reserved. This program and the accompanying materials are\r
   licensed and made available under the terms and conditions of\r
   the BSD License which accompanies this distribution.  The full\r
@@ -37,14 +37,14 @@ typedef struct {
 \r
 /**\r
   Assert the validity of a PCI Segment address.\r
-  A valid PCI address should not contain 1's in bits 31:28\r
+  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r
 \r
   @param  A The address to validate.\r
   @param  M Additional bits to assert to be zero.\r
 \r
 **/\r
 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
-  ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
+  ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
 \r
 /**\r
   Translate PCI Lib address into format of PCI Root Bridge I/O Protocol\r