1. BaseSmbusLib: Make SmbusReadDataByte() & SmbusWriteBlock() function well by re...

	2. BaseMemoryLibMmx for X64: Make CopyMem() be reentrant by saving Mm0 to r10.
	3. DxeCorePerformanceLib: Fix some typo to save build error of that library instance.
	4. Remove the orphanage definition of gEfiPerformanceProtocolGuid

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@859 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/EdkModulePkg/EdkModulePkg.spd b/EdkModulePkg/EdkModulePkg.spd
index 0f0556b80ddec41f570ca8846c5b96cc8a0f6b65..84234060d17df4cc8008ffb8a649640d8d766706 100644 (file)
--- a/EdkModulePkg/EdkModulePkg.spd
+++ b/EdkModulePkg/EdkModulePkg.spd
@@ -427,11 +427,6 @@
       <GuidValue>125F2DE1-FB85-440C-A54C-4D99358A8D38</GuidValue>\r
       <HelpText/>\r
     </Entry>\r
       <GuidValue>125F2DE1-FB85-440C-A54C-4D99358A8D38</GuidValue>\r
       <HelpText/>\r
     </Entry>\r

-    <Entry Name="Performance">\r
-      <C_Name>gEfiPerformanceProtocolGuid</C_Name>\r
-      <GuidValue>FFECFFFF-923C-14D2-9E3F-22A0C969563B</GuidValue>\r
-      <HelpText/>\r
-    </Entry>\r

     <Entry Name="PxeDhcp4">\r
       <C_Name>gEfiPxeDhcp4ProtocolGuid</C_Name>\r
       <GuidValue>03C4E624-AC28-11D3-9A2D-0090293FC14D</GuidValue>\r
     <Entry Name="PxeDhcp4">\r
       <C_Name>gEfiPxeDhcp4ProtocolGuid</C_Name>\r
       <GuidValue>03C4E624-AC28-11D3-9A2D-0090293FC14D</GuidValue>\r

diff --git a/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c b/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
index d2417234abaefbffcd58981845b1104b18ec7171..5874902e2e37c0f6521a6bc3bb08a06887ca4bd7 100644 (file)
--- a/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
+++ b/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
@@ -214,7 +214,6 @@ StartGauge (
   UINTN                     GaugeDataSize;\r
   UINTN                     OldGaugeDataSize;\r
   GAUGE_DATA_HEADER         *OldGaugeData;\r
   UINTN                     GaugeDataSize;\r
   UINTN                     OldGaugeDataSize;\r
   GAUGE_DATA_HEADER         *OldGaugeData;\r

-  EFI_STATUS                Status;\r

   UINT32                    Index;\r
 \r
   Index = mGaugeData->NumberOfEntries;\r
   UINT32                    Index;\r
 \r
   Index = mGaugeData->NumberOfEntries;\r


@@ -230,7 +229,7 @@ StartGauge (
     \r
     mGaugeData = AllocateZeroPool (GaugeDataSize);\r
     if (mGaugeData == NULL) {\r
     \r
     mGaugeData = AllocateZeroPool (GaugeDataSize);\r
     if (mGaugeData == NULL) {\r

-      return EFI_OUT_OF_MEMORY;\r
+      return EFI_OUT_OF_RESOURCES;\r

     }\r
     //\r
     // Initialize new data arry and migrate old data one. \r
     }\r
     //\r
     // Initialize new data arry and migrate old data one. \r


@@ -425,7 +424,6 @@ DxeCorePerformanceLibConstructor (
   //\r
   // Install the protocol interfaces.\r
   //\r
   //\r
   // Install the protocol interfaces.\r
   //\r

-  Handle = NULL;\r

   Status = gBS->InstallProtocolInterface (\r
                   &mHandle,\r
                   &gPerformanceProtocolGuid,\r
   Status = gBS->InstallProtocolInterface (\r
                   &mHandle,\r
                   &gPerformanceProtocolGuid,\r

diff --git a/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.msa b/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.msa
index d217bdff5e76438fc9ddae6f3e6decdc2e3a2fbd..059c1f83fd646d88c2f4864482e6ead54065ef6f 100644 (file)
--- a/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.msa
+++ b/EdkModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.msa
@@ -46,6 +46,9 @@
     <LibraryClass Usage="ALWAYS_CONSUMED">\r
       <Keyword>UefiBootServicesTableLib</Keyword>\r
     </LibraryClass>\r
     <LibraryClass Usage="ALWAYS_CONSUMED">\r
       <Keyword>UefiBootServicesTableLib</Keyword>\r
     </LibraryClass>\r

+    <LibraryClass Usage="ALWAYS_CONSUMED">\r
+      <Keyword>MemoryAllocationLib</Keyword>\r
+    </LibraryClass>\r

   </LibraryClassDefinitions>\r
   <SourceFiles>\r
     <Filename>DxeCorePerformanceLib.c</Filename>\r
   </LibraryClassDefinitions>\r
   <SourceFiles>\r
     <Filename>DxeCorePerformanceLib.c</Filename>\r

diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.asm b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.asm
index 372c36520381d00f9b176a5e66fbec5aced90f94..801cf92750aee136041032719d38fcf64ae64039 100644 (file)
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.asm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.asm
@@ -46,6 +46,7 @@ InternalMemCopyMem  PROC    USES    rsi rdi
     and     r8, 7\r
     shr     rcx, 3                      ; rcx <- # of Qwords to copy\r
     jz      @CopyBytes\r
     and     r8, 7\r
     shr     rcx, 3                      ; rcx <- # of Qwords to copy\r
     jz      @CopyBytes\r

+    DB      49h, 0fh, 7eh, 0c2h         ; movq    r10,  mm0    ; save mm0\r

 @@:\r
     DB      48h, 0fh, 6fh, 06h          ; movq    mm0, [rsi]\r
     DB      48h, 0fh, 0e7h, 07h         ; movntq  [rdi], mm0\r
 @@:\r
     DB      48h, 0fh, 6fh, 06h          ; movq    mm0, [rsi]\r
     DB      48h, 0fh, 0e7h, 07h         ; movntq  [rdi], mm0\r


@@ -53,6 +54,7 @@ InternalMemCopyMem  PROC    USES    rsi rdi
     add     rdi, 8\r
     loop    @B\r
     mfence\r
     add     rdi, 8\r
     loop    @B\r
     mfence\r

+    DB      49h, 0fh, 6eh, 0c2h          ; movq    mm0, r10    ; restore mm0\r

     jmp     @CopyBytes\r
 @CopyBackward:\r
     mov     rdi, r9                     ; rdi <- End of Destination\r
     jmp     @CopyBytes\r
 @CopyBackward:\r
     mov     rdi, r9                     ; rdi <- End of Destination\r

diff --git a/MdePkg/Library/BaseSmbusLib/SmbusLib.c b/MdePkg/Library/BaseSmbusLib/SmbusLib.c
index 39fa7e6f375907e5c6e913b48fe41568b968c46a..16ae2fa279c13d19c81a3fe628a7ae1e97308068 100644 (file)
--- a/MdePkg/Library/BaseSmbusLib/SmbusLib.c
+++ b/MdePkg/Library/BaseSmbusLib/SmbusLib.c
@@ -25,10 +25,10 @@
 //\r
 // Replaced by PCD\r
 //\r
 //\r
 // Replaced by PCD\r
 //\r

-#define ICH_SMBUS_BASE_ADDRESS               0xEFA0\r
+#define ICH_SMBUS_IO_BASE_ADDRESS               0xEFA0\r

 \r
 /**\r
 \r
 /**\r

-  Reads an 8-bit SMBUS register on ICH.\r
+  Reads an 8-bit register on ICH SMBUS controller.\r

 \r
   This internal function reads an SMBUS register specified by Offset.\r
 \r
 \r
   This internal function reads an SMBUS register specified by Offset.\r
 \r


@@ -42,11 +42,11 @@ InternalSmBusIoRead8 (
   IN UINTN      Offset\r
   )\r
 {\r
   IN UINTN      Offset\r
   )\r
 {\r

-  return IoRead8 (ICH_SMBUS_BASE_ADDRESS + Offset);\r
+  return IoRead8 (ICH_SMBUS_IO_BASE_ADDRESS + Offset);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Writes an 8-bit SMBUS register on ICH.\r
+  Writes an 8-bit register on ICH SMBUS controller.\r

 \r
   This internal function writes an SMBUS register specified by Offset.\r
 \r
 \r
   This internal function writes an SMBUS register specified by Offset.\r
 \r


@@ -62,7 +62,7 @@ InternalSmBusIoWrite8 (
   IN UINT8      Value\r
   )\r
 {\r
   IN UINT8      Value\r
   )\r
 {\r

-  return IoWrite8 (ICH_SMBUS_BASE_ADDRESS + Offset, Value);\r
+  return IoWrite8 (ICH_SMBUS_IO_BASE_ADDRESS + Offset, Value);\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -89,31 +89,29 @@ InternalSmBusAcquire (
     return RETURN_TIMEOUT;\r
   } else if ((HostStatus & SMBUS_B_HOST_BUSY) != 0) {\r
     //\r
     return RETURN_TIMEOUT;\r
   } else if ((HostStatus & SMBUS_B_HOST_BUSY) != 0) {\r
     //\r

-    // Clear Status Register and exit\r
+    // Clear host status register and exit.\r

     //\r
     InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
     return RETURN_TIMEOUT;\r
   }\r
   //\r
     //\r
     InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
     return RETURN_TIMEOUT;\r
   }\r
   //\r

-  // Clear byte pointer of 32-byte buffer.\r
-  //\r
-  InternalSmBusIoRead8 (SMBUS_R_HST_CTL);\r
+  // Clear out any odd status information (Will Not Clear In Use).\r

   //\r
   //\r

-  // Clear BYTE_DONE status\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_BYTE_DONE_STS);\r
+  InternalSmBusIoWrite8 (SMBUS_R_HST_STS, HostStatus);\r

   \r
   return RETURN_SUCCESS;\r
 }\r
 \r
 /**\r
   \r
   return RETURN_SUCCESS;\r
 }\r
 \r
 /**\r

-  Waits until the completion of SMBUS transaction.\r
+  Starts the SMBUS transaction and waits until the end.\r

 \r
 \r

-  This internal function waits until the transaction of SMBUS is over\r
-  by polling the INTR bit of Host status register.\r
+  This internal function start the SMBUS transaction and waits until the transaction\r
+  of SMBUS is over by polling the INTR bit of Host status register.\r

   If the SMBUS is not available, RETURN_TIMEOUT is returned;\r
   Otherwise, it performs some basic initializations and returns\r
   If the SMBUS is not available, RETURN_TIMEOUT is returned;\r
   Otherwise, it performs some basic initializations and returns\r

-  RETURN_SUCCESS. \r
+  RETURN_SUCCESS.\r
+  \r
+  @param  HostControl         The Host control command to start SMBUS transaction.\r

 \r
   @retval RETURN_SUCCESS      The SMBUS command was executed successfully.\r
   @retval RETURN_CRC_ERROR    The checksum is not correct (PEC is incorrect).\r
 \r
   @retval RETURN_SUCCESS      The SMBUS command was executed successfully.\r
   @retval RETURN_CRC_ERROR    The checksum is not correct (PEC is incorrect).\r


@@ -124,18 +122,21 @@ InternalSmBusAcquire (
 \r
 **/\r
 RETURN_STATUS\r
 \r
 **/\r
 RETURN_STATUS\r

-InternalSmBusWait (\r
-  VOID \r
+InternalSmBusStart (\r
+  IN  UINT8                   HostControl\r

   )\r
 {\r
   UINT8   HostStatus;\r
   UINT8   AuxiliaryStatus;\r
   )\r
 {\r
   UINT8   HostStatus;\r
   UINT8   AuxiliaryStatus;\r

-  BOOLEAN First;\r
-  First = TRUE;\r
+\r
+  //\r
+  // Set Host Control Register (Initiate Operation, Interrupt disabled).\r
+  //\r
+  InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);\r

 \r
   do {\r
     //\r
 \r
   do {\r
     //\r

-    // Poll INTR bit of host status register.\r
+    // Poll INTR bit of Host Status Register.\r

     //\r
     HostStatus = InternalSmBusIoRead8 (SMBUS_R_HST_STS);\r
   } while ((HostStatus & (SMBUS_B_INTR | SMBUS_B_ERROR | SMBUS_B_BYTE_DONE_STS)) == 0);\r
     //\r
     HostStatus = InternalSmBusIoRead8 (SMBUS_R_HST_STS);\r
   } while ((HostStatus & (SMBUS_B_INTR | SMBUS_B_ERROR | SMBUS_B_BYTE_DONE_STS)) == 0);\r


@@ -144,11 +145,11 @@ InternalSmBusWait (
     return RETURN_SUCCESS;\r
   }\r
   //\r
     return RETURN_SUCCESS;\r
   }\r
   //\r

-  // Clear error bits of host status register\r
+  // Clear error bits of Host Status Register.\r

   //\r
   InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_ERROR);\r
   //\r
   //\r
   InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_ERROR);\r
   //\r

-  // Read auxiliary status register to judge CRC error.\r
+  // Read Auxiliary Status Register to judge CRC error.\r

   //\r
   AuxiliaryStatus = InternalSmBusIoRead8 (SMBUS_R_AUX_STS);\r
   if ((AuxiliaryStatus & SMBUS_B_CRCE) != 0) {\r
   //\r
   AuxiliaryStatus = InternalSmBusIoRead8 (SMBUS_R_AUX_STS);\r
   if ((AuxiliaryStatus & SMBUS_B_CRCE) != 0) {\r


@@ -159,64 +160,85 @@ InternalSmBusWait (
 }\r
 \r
 /**\r
 }\r
 \r
 /**\r

-  Executes an SMBUS quick read/write command.\r
+  Executes an SMBUS quick, byte or word command.\r

 \r
 \r

-  This internal function executes an SMBUS quick read/write command\r
-  on the SMBUS device specified by SmBusAddress.\r
-  Only the SMBUS slave address field of SmBusAddress is required.\r
+  This internal function executes an SMBUS quick, byte or word commond.\r

   If Status is not NULL, then the status of the executed command is returned in Status.\r
 \r
   If Status is not NULL, then the status of the executed command is returned in Status.\r
 \r

+  @param  HostControl     The value of Host Control Register to set.  \r

   @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
                           SMBUS Command, SMBUS Data Length, and PEC.\r
   @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
                           SMBUS Command, SMBUS Data Length, and PEC.\r

+  @param  Value           The byte/word write to the SMBUS.\r

   @param  Status          Return status for the executed command.\r
                           This is an optional parameter and may be NULL.\r
 \r
   @param  Status          Return status for the executed command.\r
                           This is an optional parameter and may be NULL.\r
 \r

+  @return The byte/word read from the SMBUS.\r
+\r

 **/\r
 **/\r

-VOID\r
-EFIAPI\r
-InternalSmBusQuick (\r
+UINT16\r
+InternalSmBusNonBlock (\r
+  IN  UINT8                     HostControl,\r

   IN  UINTN                     SmBusAddress,\r
   IN  UINTN                     SmBusAddress,\r

-  OUT RETURN_STATUS             *Status       OPTIONAL\r
+  IN  UINT16                    Value,\r
+  OUT RETURN_STATUS             *Status\r

   )\r
 {\r
   )\r
 {\r

-  RETURN_STATUS   ReturnStatus;\r
+  RETURN_STATUS                 ReturnStatus;\r
+  UINT8                         AuxiliaryControl;\r

 \r
 \r

+  //\r
+  // Try to acquire the ownership of ICH SMBUS.\r
+  //\r

   ReturnStatus = InternalSmBusAcquire ();\r
   if (RETURN_ERROR (ReturnStatus)) {\r
     goto Done;\r
   }\r
   ReturnStatus = InternalSmBusAcquire ();\r
   if (RETURN_ERROR (ReturnStatus)) {\r
     goto Done;\r
   }\r

- \r

   //\r
   //\r

-  // Set Command register\r
+  // Set the appropriate Host Control Register and auxiliary Control Register.\r

   //\r
   //\r

-  InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, 0);\r
+  AuxiliaryControl = 0;\r
+  if (SMBUS_LIB_PEC (SmBusAddress)) {\r
+    AuxiliaryControl |= SMBUS_B_AAC;\r
+    HostControl      |= SMBUS_B_PEC_EN;\r
+  }\r
+  //\r
+  // Set Host Commond Register.\r
+  //\r
+  InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
+  //\r
+  // Write value to Host Data 0 and Host Data 1 Registers.\r
+  //\r
+  InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) Value);\r
+  InternalSmBusIoWrite8 (SMBUS_R_HST_D1, (UINT8) (Value >> 8));\r

   //\r
   //\r

-  // Set Auxiliary Control register\r
+  // Set Auxiliary Control Regiester.\r

   //\r
   //\r

-  InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, 0);\r
+  InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);\r

   //\r
   //\r

-  // Set SMBus slave address for the device to send/receive from\r
+  // Set SMBUS slave address for the device to send/receive from.\r

   //\r
   InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
   //\r
   //\r
   InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
   //\r

-  // Set Control Register (Initiate Operation, Interrupt disabled)\r
+  // Start the SMBUS transaction and wait for the end.\r

   //\r
   //\r

-  InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, SMBUS_V_SMB_CMD_QUICK + SMBUS_B_START);\r
-\r
+  ReturnStatus = InternalSmBusStart (HostControl);\r

   //\r
   //\r

-  // Wait for the end\r
+  // Read value from Host Data 0 and Host Data 1 Registers.\r

   //\r
   //\r

-  ReturnStatus = InternalSmBusWait ();\r
-\r
+  Value  = InternalSmBusIoRead8 (SMBUS_R_HST_D1) << 8;\r
+  Value |= InternalSmBusIoRead8 (SMBUS_R_HST_D0);\r

   //\r
   //\r

-  // Clear status register and exit\r
+  // Clear Host Status Register and Auxiliary Status Register.\r

   //\r
   //\r

-  InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);;\r
+  InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
+  InternalSmBusIoWrite8 (SMBUS_R_AUX_STS, SMBUS_B_CRCE);\r

 \r
 Done:\r
   if (Status != NULL) {\r
     *Status = ReturnStatus;\r
   }\r
 \r
 Done:\r
   if (Status != NULL) {\r
     *Status = ReturnStatus;\r
   }\r

+\r
+  return Value;\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -248,7 +270,12 @@ SmBusQuickRead (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  InternalSmBusQuick (SmBusAddress | SMBUS_B_READ, Status);\r
+  InternalSmBusNonBlock (\r
+    SMBUS_V_SMB_CMD_QUICK,\r
+    SmBusAddress | SMBUS_B_READ,\r
+    0,\r
+    Status\r
+    );\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -280,88 +307,12 @@ SmBusQuickWrite (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  InternalSmBusQuick (SmBusAddress | SMBUS_B_WRITE, Status);\r
-}\r
-\r
-/**\r
-  Executes an SMBUS byte or word command.\r
-\r
-  This internal function executes an .\r
-  Only the SMBUS slave address field of SmBusAddress is required.\r
-  If Status is not NULL, then the status of the executed command is returned in Status.\r
-\r
-  @param  HostControl     The value of Host Control Register to set.  \r
-  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
-                          SMBUS Command, SMBUS Data Length, and PEC.\r
-  @param  Value           The byte/word write to the SMBUS.\r
-  @param  Status          Return status for the executed command.\r
-                          This is an optional parameter and may be NULL.\r
-\r
-  @return The byte/word read from the SMBUS.\r
-\r
-**/\r
-UINT16\r
-InternalSmBusByteWord (\r
-  IN  UINT8                     HostControl,\r
-  IN  UINTN                     SmBusAddress,\r
-  IN  UINT16                    Value,\r
-  OUT RETURN_STATUS             *Status\r
-  )\r
-{\r
-  RETURN_STATUS                 ReturnStatus;\r
-  UINT8                         AuxiliaryControl;\r
-\r
-  ReturnStatus = InternalSmBusAcquire ();\r
-  if (RETURN_ERROR (ReturnStatus)) {\r
-    goto Done;\r
-  }\r
-\r
-  AuxiliaryControl = 0;\r
-  if (SMBUS_LIB_PEC (SmBusAddress)) {\r
-    AuxiliaryControl |= SMBUS_B_AAC;\r
-    HostControl      |= SMBUS_B_PEC_EN;\r
-  }\r
- \r
-  //\r
-  // Set commond register\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
-\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) Value);\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_D1, (UINT8) (Value >> 8));\r
-\r
-  //\r
-  // Set Auxiliary Control Regiester.\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);\r
-  //\r
-  // Set SMBus slave address for the device to send/receive from.\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
-  //\r
-  // Set Control Register (Initiate Operation, Interrupt disabled)\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);\r
-\r
-  //\r
-  // Wait for the end\r
-  //\r
-  ReturnStatus = InternalSmBusWait ();\r
- \r
-  Value  = InternalSmBusIoRead8 (SMBUS_R_HST_D1) << 8;\r
-  Value |= InternalSmBusIoRead8 (SMBUS_R_HST_D0);\r
-\r
-  //\r
-  // Clear status register and exit\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);;\r
-\r
-Done:\r
-  if (Status != NULL) {\r
-    *Status = ReturnStatus;\r
-  }\r
-\r
-  return Value;\r
+  InternalSmBusNonBlock (\r
+    SMBUS_V_SMB_CMD_QUICK,\r
+    SmBusAddress | SMBUS_B_WRITE,\r
+    0,\r
+    Status\r
+    );\r

 }\r
 \r
 /**\r
 }\r
 \r
 /**\r


@@ -394,7 +345,7 @@ SmBusReceiveByte (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return (UINT8) InternalSmBusByteWord (\r
+  return (UINT8) InternalSmBusNonBlock (\r

                    SMBUS_V_SMB_CMD_BYTE,\r
                    SmBusAddress | SMBUS_B_READ,\r
                    0,\r
                    SMBUS_V_SMB_CMD_BYTE,\r
                    SmBusAddress | SMBUS_B_READ,\r
                    0,\r


@@ -434,7 +385,7 @@ SmBusSendByte (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return (UINT8) InternalSmBusByteWord (\r
+  return (UINT8) InternalSmBusNonBlock (\r

                    SMBUS_V_SMB_CMD_BYTE,\r
                    SmBusAddress | SMBUS_B_WRITE,\r
                    Value,\r
                    SMBUS_V_SMB_CMD_BYTE,\r
                    SmBusAddress | SMBUS_B_WRITE,\r
                    Value,\r


@@ -470,7 +421,7 @@ SmBusReadDataByte (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return (UINT8) InternalSmBusByteWord (\r
+  return (UINT8) InternalSmBusNonBlock (\r

                    SMBUS_V_SMB_CMD_BYTE_DATA,\r
                    SmBusAddress | SMBUS_B_READ,\r
                    0,\r
                    SMBUS_V_SMB_CMD_BYTE_DATA,\r
                    SmBusAddress | SMBUS_B_READ,\r
                    0,\r


@@ -509,7 +460,7 @@ SmBusWriteDataByte (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return (UINT8) InternalSmBusByteWord (\r
+  return (UINT8) InternalSmBusNonBlock (\r

                    SMBUS_V_SMB_CMD_BYTE_DATA,\r
                    SmBusAddress | SMBUS_B_WRITE,\r
                    Value,\r
                    SMBUS_V_SMB_CMD_BYTE_DATA,\r
                    SmBusAddress | SMBUS_B_WRITE,\r
                    Value,\r


@@ -545,7 +496,7 @@ SmBusReadDataWord (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return InternalSmBusByteWord (\r
+  return InternalSmBusNonBlock (\r

            SMBUS_V_SMB_CMD_WORD_DATA,\r
            SmBusAddress | SMBUS_B_READ,\r
            0,\r
            SMBUS_V_SMB_CMD_WORD_DATA,\r
            SmBusAddress | SMBUS_B_READ,\r
            0,\r


@@ -584,7 +535,7 @@ SmBusWriteDataWord (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return InternalSmBusByteWord (\r
+  return InternalSmBusNonBlock (\r

            SMBUS_V_SMB_CMD_WORD_DATA,\r
            SmBusAddress | SMBUS_B_WRITE,\r
            Value,\r
            SMBUS_V_SMB_CMD_WORD_DATA,\r
            SmBusAddress | SMBUS_B_WRITE,\r
            Value,\r


@@ -623,7 +574,7 @@ SmBusProcessCall (
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r
   ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
   ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
 \r

-  return InternalSmBusByteWord (\r
+  return InternalSmBusNonBlock (\r

            SMBUS_V_SMB_CMD_PROCESS_CALL,\r
            SmBusAddress | SMBUS_B_WRITE,\r
            Value,\r
            SMBUS_V_SMB_CMD_PROCESS_CALL,\r
            SmBusAddress | SMBUS_B_WRITE,\r
            Value,\r


@@ -666,61 +617,77 @@ InternalSmBusBlock (
   UINTN                         Index;\r
   UINTN                         BytesCount;\r
   UINT8                         AuxiliaryControl;\r
   UINTN                         Index;\r
   UINTN                         BytesCount;\r
   UINT8                         AuxiliaryControl;\r

-\r
+  \r

   BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);\r
   BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);\r

-\r
+  //\r
+  // Try to acquire the ownership of ICH SMBUS.\r
+  //\r

   ReturnStatus = InternalSmBusAcquire ();\r
   if (RETURN_ERROR (ReturnStatus)) {\r
     goto Done;\r
   }\r
   ReturnStatus = InternalSmBusAcquire ();\r
   if (RETURN_ERROR (ReturnStatus)) {\r
     goto Done;\r
   }\r

-  \r
+  //\r
+  // Set the appropriate Host Control Register and auxiliary Control Register.\r
+  //\r

   AuxiliaryControl = SMBUS_B_E32B;\r
   if (SMBUS_LIB_PEC (SmBusAddress)) {\r
     AuxiliaryControl |= SMBUS_B_AAC;\r
     HostControl      |= SMBUS_B_PEC_EN;\r
   }\r
   AuxiliaryControl = SMBUS_B_E32B;\r
   if (SMBUS_LIB_PEC (SmBusAddress)) {\r
     AuxiliaryControl |= SMBUS_B_AAC;\r
     HostControl      |= SMBUS_B_PEC_EN;\r
   }\r

-\r
+  //\r
+  // Set Host Command Register.\r
+  //\r

   InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
   InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r

-\r
-  InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) BytesCount);\r
+  //\r
+  // Set Auxiliary Control Regiester.\r
+  //\r
+  InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);\r
+  //\r
+  // Clear byte pointer of 32-byte buffer.\r
+  //\r
+  InternalSmBusIoRead8 (SMBUS_R_HST_CTL);\r

 \r
   if (WriteBuffer != NULL) {\r
 \r
   if (WriteBuffer != NULL) {\r

+    //\r
+    // Write the number of block to Host Block Data Byte Register.\r
+    //\r
+    InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) BytesCount);\r
+    //\r
+    // Write data block to Host Block Data Register.\r
+    //\r

     for (Index = 0; Index < BytesCount; Index++) {\r
       InternalSmBusIoWrite8 (SMBUS_R_HOST_BLOCK_DB, WriteBuffer[Index]);\r
     }\r
   }\r
   //\r
     for (Index = 0; Index < BytesCount; Index++) {\r
       InternalSmBusIoWrite8 (SMBUS_R_HOST_BLOCK_DB, WriteBuffer[Index]);\r
     }\r
   }\r
   //\r

-  // Set Auxiliary Control Regiester.\r
-  //\r
-  InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);\r
-  //\r
-  // Set SMBus slave address for the device to send/receive from\r
+  // Set SMBUS slave address for the device to send/receive from.\r

   //\r
   InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
   //\r
   //\r
   InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
   //\r

-  // Set Control Register (Initiate Operation, Interrupt disabled)\r
+  // Start the SMBUS transaction and wait for the end.\r

   //\r
   //\r

-  InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);\r
-\r
-  //\r
-  // Wait for the end\r
-  //\r
-  ReturnStatus = InternalSmBusWait ();\r
+  ReturnStatus = InternalSmBusStart (HostControl);\r

   if (RETURN_ERROR (ReturnStatus)) {\r
     goto Done;\r
   }\r
 \r
   if (RETURN_ERROR (ReturnStatus)) {\r
     goto Done;\r
   }\r
 \r

-  BytesCount = InternalSmBusIoRead8 (SMBUS_R_HST_D0);\r

   if (ReadBuffer != NULL) {\r
   if (ReadBuffer != NULL) {\r

+    //\r
+    // Read the number of block from host block data byte register.\r
+    //\r
+    BytesCount = InternalSmBusIoRead8 (SMBUS_R_HST_D0);\r
+    //\r
+    // Write data block from Host Block Data Register.\r
+    //\r

     for (Index = 0; Index < BytesCount; Index++) {\r
       ReadBuffer[Index] = InternalSmBusIoRead8 (SMBUS_R_HOST_BLOCK_DB);\r
     }\r
   }\r
     for (Index = 0; Index < BytesCount; Index++) {\r
       ReadBuffer[Index] = InternalSmBusIoRead8 (SMBUS_R_HOST_BLOCK_DB);\r
     }\r
   }\r

-\r

   //\r
   //\r

-  // Clear status register and exit\r
+  // Clear Host Status Register and Auxiliary Status Register.\r

   //\r
   InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
   //\r
   InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r

+  InternalSmBusIoWrite8 (SMBUS_R_AUX_STS, SMBUS_B_CRCE);\r

 \r
 Done:\r
   if (Status != NULL) {\r
 \r
 Done:\r
   if (Status != NULL) {\r