MdePkg/include: Add DMAR SATC Table Definition

SoC Integrated Address Translation Cache (SATC) reporting structure is one
of the Remapping Structure, which is imported since Intel(R) Virtualization
Technology for Directed I/O (VT-D) Architecture Specification v3.2.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3109

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Kowalewski Robert <robert.kowalewski@intel.com>
Cc: Feng Roger <roger.feng@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

diff --git a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
index 7c50dc972e71cf8e7bf7e8f28ccaaea0e30b3b8a..48f6959fec441aa3adbce0befab5a9d77209ca1c 100644 (file)
--- a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
+++ b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
@@ -2,13 +2,13 @@
   DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)\r
   Virtualization Technology for Directed I/O (VT-D) Architecture Specification.\r
 \r
-  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
   @par Revision Reference:\r
     - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture\r
-      Specification v2.5, Dated November 2017.\r
-      http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf\r
+      Specification v3.2, Dated October 2020.\r
+      https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf\r
 \r
   @par Glossary:\r
     - HPET - High Precision Event Timer\r
@@ -39,6 +39,7 @@
 #define EFI_ACPI_DMAR_TYPE_ATSR                   0x02\r
 #define EFI_ACPI_DMAR_TYPE_RHSA                   0x03\r
 #define EFI_ACPI_DMAR_TYPE_ANDD                   0x04\r
+#define EFI_ACPI_DMAR_TYPE_SATC                   0x05\r
 ///@}\r
 \r
 ///\r
@@ -216,6 +217,32 @@ typedef struct {
   UINT8                           AcpiDeviceNumber;\r
 } EFI_ACPI_DMAR_ANDD_HEADER;\r
 \r
+/**\r
+  An SoC Integrated Address Translation Cache (SATC) reporting structure is\r
+  defined in section 8.8.\r
+**/\r
+typedef struct {\r
+  EFI_ACPI_DMAR_STRUCTURE_HEADER  Header;\r
+  /**\r
+    - Bit[0]: ATC_REQUIRED:\r
+              - If Set, indicates that every SoC integrated device enumerated\r
+                in this table has a functional requirement to enable its ATC\r
+                (via the ATS capability) for device operation.\r
+              - If Clear, any device enumerated in this table can operate when\r
+                its respective ATC is not enabled (albeit with reduced\r
+                performance or functionality).\r
+    - Bits[7:1] Reserved.\r
+  **/\r
+  UINT8                           Flags;\r
+  UINT8                           Reserved;\r
+  ///\r
+  /// The PCI Segment associated with this SATC structure. All SoC integrated\r
+  /// devices within a PCI segment with same value for Flags field must be\r
+  /// enumerated in the same SATC structure.\r
+  ///\r
+  UINT16                          SegmentNumber;\r
+} EFI_ACPI_DMAR_SATC_HEADER;\r
+\r
 /**\r
   DMA Remapping Reporting Structure Header as defined in section 8.1\r
   This header will be followed by list of Remapping Structures listed below\r
@@ -224,6 +251,7 @@ typedef struct {
     - Root Port ATS Capability Reporting (ATSR)\r
     - Remapping Hardware Static Affinity (RHSA)\r
     - ACPI Name-space Device Declaration (ANDD)\r
+    - SoC Integrated Address Translation Cache reporting (SATC)\r
   These structure types must by reported in numerical order.\r
   i.e., All remapping structures of type 0 (DRHD) enumerated before remapping\r
   structures of type 1 (RMRR), and so forth.\r