-///** @file\r
-// IPF Processor Defines for assembly code\r
-//\r
-// @note\r
-// This file is included by assembly files as well. The assmber can NOT deal\r
-// with /* */ commnets this is why this file is commented not following the\r
-// coding standard\r
-//\r
-//Copyright (c) 2006, Intel Corporation\r
-//All rights reserved. This program and the accompanying materials\r
-//are licensed and made available under the terms and conditions of the BSD License\r
-//which accompanies this distribution. The full text of the license may be found at\r
-//http://opensource.org/licenses/bsd-license.php\r
-//\r
-//THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-//WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//Module Name: IpfDefines.h\r
-//\r
-//**/\r
-\r
-#ifndef _IPFDEFINES_H\r
-#define _IPFDEFINES_H\r
-\r
-//\r
-// IPI DElivery Methods\r
-//\r
-#define IPI_INT_DELIVERY 0x0\r
-#define IPI_PMI_DELIVERY 0x2\r
-#define IPI_NMI_DELIVERY 0x4\r
-#define IPI_INIT_DELIVERY 0x5\r
-#define IPI_ExtINT_DELIVERY 0x7\r
-\r
-//\r
-// Define Itanium-based system registers.\r
-//\r
-// Define Itanium-based system register bit field offsets.\r
-//\r
-// Processor Status Register (PSR) Bit positions\r
-//\r
-// User / System mask\r
-//\r
-#define PSR_RV0 0\r
-#define PSR_BE 1\r
-#define PSR_UP 2\r
-#define PSR_AC 3\r
-#define PSR_MFL 4\r
-#define PSR_MFH 5\r
-\r
-//\r
-// PSR bits 6-12 reserved (must be zero)\r
-//\r
-#define PSR_MBZ0 6\r
-#define PSR_MBZ0_V 0x1ffUL L\r
-\r
-//\r
-// System only mask\r
-//\r
-#define PSR_IC 13\r
-#define PSR_IC_MASK (1 << 13)\r
-#define PSR_I 14\r
-#define PSR_PK 15\r
-#define PSR_MBZ1 16\r
-#define PSR_MBZ1_V 0x1UL L\r
-#define PSR_DT 17\r
-#define PSR_DFL 18\r
-#define PSR_DFH 19\r
-#define PSR_SP 20\r
-#define PSR_PP 21\r
-#define PSR_DI 22\r
-#define PSR_SI 23\r
-#define PSR_DB 24\r
-#define PSR_LP 25\r
-#define PSR_TB 26\r
-#define PSR_RT 27\r
-\r
-//\r
-// PSR bits 28-31 reserved (must be zero)\r
-//\r
-#define PSR_MBZ2 28\r
-#define PSR_MBZ2_V 0xfUL L\r
-\r
-//\r
-// Neither mask\r
-//\r
-#define PSR_CPL 32\r
-#define PSR_CPL_LEN 2\r
-#define PSR_IS 34\r
-#define PSR_MC 35\r
-#define PSR_IT 36\r
-#define PSR_IT_MASK 0x1000000000\r
-#define PSR_ID 37\r
-#define PSR_DA 38\r
-#define PSR_DD 39\r
-#define PSR_SS 40\r
-#define PSR_RI 41\r
-#define PSR_RI_LEN 2\r
-#define PSR_ED 43\r
-#define PSR_BN 44\r
-\r
-//\r
-// PSR bits 45-63 reserved (must be zero)\r
-//\r
-#define PSR_MBZ3 45\r
-#define PSR_MBZ3_V 0xfffffULL\r
-\r
-//\r
-// Floating Point Status Register (FPSR) Bit positions\r
-//\r
-//\r
-// Traps\r
-//\r
-#define FPSR_VD 0\r
-#define FPSR_DD 1\r
-#define FPSR_ZD 2\r
-#define FPSR_OD 3\r
-#define FPSR_UD 4\r
-#define FPSR_ID 5\r
-\r
-//\r
-// Status Field 0 - Controls\r
-//\r
-#define FPSR0_FTZ0 6\r
-#define FPSR0_WRE0 7\r
-#define FPSR0_PC0 8\r
-#define FPSR0_RC0 10\r
-#define FPSR0_TD0 12\r
-\r
-//\r
-// Status Field 0 - Flags\r
-//\r
-#define FPSR0_V0 13\r
-#define FPSR0_D0 14\r
-#define FPSR0_Z0 15\r
-#define FPSR0_O0 16\r
-#define FPSR0_U0 17\r
-#define FPSR0_I0 18\r
-\r
-//\r
-// Status Field 1 - Controls\r
-//\r
-#define FPSR1_FTZ0 19\r
-#define FPSR1_WRE0 20\r
-#define FPSR1_PC0 21\r
-#define FPSR1_RC0 23\r
-#define FPSR1_TD0 25\r
-\r
-//\r
-// Status Field 1 - Flags\r
-//\r
-#define FPSR1_V0 26\r
-#define FPSR1_D0 27\r
-#define FPSR1_Z0 28\r
-#define FPSR1_O0 29\r
-#define FPSR1_U0 30\r
-#define FPSR1_I0 31\r
-\r
-//\r
-// Status Field 2 - Controls\r
-//\r
-#define FPSR2_FTZ0 32\r
-#define FPSR2_WRE0 33\r
-#define FPSR2_PC0 34\r
-#define FPSR2_RC0 36\r
-#define FPSR2_TD0 38\r
-\r
-//\r
-// Status Field 2 - Flags\r
-//\r
-#define FPSR2_V0 39\r
-#define FPSR2_D0 40\r
-#define FPSR2_Z0 41\r
-#define FPSR2_O0 42\r
-#define FPSR2_U0 43\r
-#define FPSR2_I0 44\r
-\r
-//\r
-// Status Field 3 - Controls\r
-//\r
-#define FPSR3_FTZ0 45\r
-#define FPSR3_WRE0 46\r
-#define FPSR3_PC0 47\r
-#define FPSR3_RC0 49\r
-#define FPSR3_TD0 51\r
-\r
-//\r
-// Status Field 0 - Flags\r
-//\r
-#define FPSR3_V0 52\r
-#define FPSR3_D0 53\r
-#define FPSR3_Z0 54\r
-#define FPSR3_O0 55\r
-#define FPSR3_U0 56\r
-#define FPSR3_I0 57\r
-\r
-//\r
-// FPSR bits 58-63 Reserved -- Must be zero\r
-//\r
-#define FPSR_MBZ0 58\r
-#define FPSR_MBZ0_V 0x3fUL L\r
-\r
-//\r
-// For setting up FPSR on kernel entry\r
-// All traps are disabled.\r
-//\r
-#define FPSR_FOR_KERNEL 0x3f\r
-\r
-#define FP_REG_SIZE 16 // 16 byte spill size\r
-#define HIGHFP_REGS_LENGTH (96 * 16)\r
-\r
-//\r
-// Define hardware Task Priority Register (TPR)\r
-//\r
-//\r
-// TPR bit positions\r
-//\r
-#define TPR_MIC 4 // Bits 0 - 3 ignored\r
-#define TPR_MIC_LEN 4\r
-#define TPR_MMI 16 // Mask Maskable Interrupt\r
-//\r
-// Define hardware Interrupt Status Register (ISR)\r
-//\r
-//\r
-// ISR bit positions\r
-//\r
-#define ISR_CODE 0\r
-#define ISR_CODE_LEN 16\r
-#define ISR_CODE_MASK 0xFFFF\r
-#define ISR_IA_VECTOR 16\r
-#define ISR_IA_VECTOR_LEN 8\r
-#define ISR_MBZ0 24\r
-#define ISR_MBZ0_V 0xff\r
-#define ISR_X 32\r
-#define ISR_W 33\r
-#define ISR_R 34\r
-#define ISR_NA 35\r
-#define ISR_SP 36\r
-#define ISR_RS 37\r
-#define ISR_IR 38\r
-#define ISR_NI 39\r
-#define ISR_MBZ1 40\r
-#define ISR_EI 41\r
-#define ISR_ED 43\r
-#define ISR_MBZ2 44\r
-#define ISR_MBZ2_V 0xfffff\r
-\r
-//\r
-// ISR codes\r
-//\r
-// For General exceptions: ISR{3:0}\r
-//\r
-#define ISR_ILLEGAL_OP 0 // Illegal operation fault\r
-#define ISR_PRIV_OP 1 // Privileged operation fault\r
-#define ISR_PRIV_REG 2 // Privileged register fauls\r
-#define ISR_RESVD_REG 3 // Reserved register/field flt\r
-#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault\r
-//\r
-// Define hardware Default Control Register (DCR)\r
-//\r
-//\r
-// DCR bit positions\r
-//\r
-#define DCR_PP 0\r
-#define DCR_BE 1\r
-#define DCR_LC 2\r
-#define DCR_MBZ0 4\r
-#define DCR_MBZ0_V 0xf\r
-#define DCR_DM 8\r
-#define DCR_DP 9\r
-#define DCR_DK 10\r
-#define DCR_DX 11\r
-#define DCR_DR 12\r
-#define DCR_DA 13\r
-#define DCR_DD 14\r
-#define DCR_DEFER_ALL 0x7f00\r
-#define DCR_MBZ1 2\r
-#define DCR_MBZ1_V 0xffffffffffffUL L\r
-\r
-//\r
-// Define hardware RSE Configuration Register\r
-//\r
-// RS Configuration (RSC) bit field positions\r
-//\r
-#define RSC_MODE 0\r
-#define RSC_PL 2\r
-#define RSC_BE 4\r
-#define RSC_MBZ0 5\r
-#define RSC_MBZ0_V 0x3ff\r
-#define RSC_LOADRS 16\r
-#define RSC_LOADRS_LEN 14\r
-#define RSC_MBZ1 30\r
-#define RSC_MBZ1_V 0x3ffffffffUL L\r
-\r
-//\r
-// RSC modes\r
-//\r
-#define RSC_MODE_LY (0x0) // Lazy\r
-#define RSC_MODE_SI (0x1) // Store intensive\r
-#define RSC_MODE_LI (0x2) // Load intensive\r
-#define RSC_MODE_EA (0x3) // Eager\r
-//\r
-// RSC Endian bit values\r
-//\r
-#define RSC_BE_LITTLE 0\r
-#define RSC_BE_BIG 1\r
-\r
-//\r
-// Define Interruption Function State (IFS) Register\r
-//\r
-// IFS bit field positions\r
-//\r
-#define IFS_IFM 0\r
-#define IFS_IFM_LEN 38\r
-#define IFS_MBZ0 38\r
-#define IFS_MBZ0_V 0x1ffffff\r
-#define IFS_V 63\r
-#define IFS_V_LEN 1\r
-\r
-//\r
-// IFS is valid when IFS_V = IFS_VALID\r
-//\r
-#define IFS_VALID 1\r
-\r
-//\r
-// Define Page Table Address (PTA)\r
-//\r
-#define PTA_VE 0\r
-#define PTA_VF 8\r
-#define PTA_SIZE 2\r
-#define PTA_SIZE_LEN 6\r
-#define PTA_BASE 15\r
-\r
-//\r
-// Define Region Register (RR)\r
-//\r
-//\r
-// RR bit field positions\r
-//\r
-#define RR_VE 0\r
-#define RR_MBZ0 1\r
-#define RR_PS 2\r
-#define RR_PS_LEN 6\r
-#define RR_RID 8\r
-#define RR_RID_LEN 24\r
-#define RR_MBZ1 32\r
-\r
-//\r
-// SAL uses region register 0 and RID of 1000\r
-//\r
-#define SAL_RID 0x1000\r
-#define SAL_RR_REG 0x0\r
-#define SAL_TR 0x0\r
-\r
-//\r
-// Total number of region registers\r
-//\r
-#define RR_SIZE 8\r
-\r
-//\r
-// Define Protection Key Register (PKR)\r
-//\r
-// PKR bit field positions\r
-//\r
-#define PKR_V 0\r
-#define PKR_WD 1\r
-#define PKR_RD 2\r
-#define PKR_XD 3\r
-#define PKR_MBZ0 4\r
-#define PKR_KEY 8\r
-#define PKR_KEY_LEN 24\r
-#define PKR_MBZ1 32\r
-\r
-#define PKR_VALID (1 << PKR_V)\r
-\r
-//\r
-// Number of protection key registers\r
-//\r
-#define PKRNUM 8\r
-\r
-//\r
-// Define Interruption TLB Insertion register (ITIR)\r
-//\r
-//\r
-// Define Translation Insertion Format (TR)\r
-//\r
-// PTE0 bit field positions\r
-//\r
-#define PTE0_P 0\r
-#define PTE0_MBZ0 1\r
-#define PTE0_MA 2\r
-#define PTE0_A 5\r
-#define PTE0_D 6\r
-#define PTE0_PL 7\r
-#define PTE0_AR 9\r
-#define PTE0_PPN 12\r
-#define PTE0_MBZ1 48\r
-#define PTE0_ED 52\r
-#define PTE0_IGN0 53\r
-\r
-//\r
-// ITIR bit field positions\r
-//\r
-#define ITIR_MBZ0 0\r
-#define ITIR_PS 2\r
-#define ITIR_PS_LEN 6\r
-#define ITIR_KEY 8\r
-#define ITIR_KEY_LEN 24\r
-#define ITIR_MBZ1 32\r
-#define ITIR_MBZ1_LEN 16\r
-#define ITIR_PPN 48\r
-#define ITIR_PPN_LEN 15\r
-#define ITIR_MBZ2 63\r
-\r
-#define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)\r
-#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)\r
-// Dirty (bit 6=1), Accessed (bit 5=1),\r
-// MA WB (bits 4-2=000), Present (bit 0=1)\r
-//\r
-// Memory access rights\r
-//\r
-#define AR_UR_KR 0x0 // user/kernel read\r
-#define AR_URX_KRX 0x1 // user/kernel read and execute\r
-#define AR_URW_KRW 0x2 // user/kernel read & write\r
-#define AR_URWX_KRWX 0x3 // user/kernel read,write&execute\r
-#define AR_UR_KRW 0x4 // user read/kernel read,write\r
-#define AR_URX_KRWX 0x5 // user read/execute, kernel all\r
-#define AR_URWX_KRW 0x6 // user all, kernel read & write\r
-#define AR_UX_KRX 0x7 // user execute only, kernel read and execute\r
-//\r
-// Memory attribute values\r
-//\r
-//\r
-// The next 4 are all cached, non-sequential & speculative, coherent\r
-//\r
-#define MA_WBU 0x0 // Write back, unordered\r
-//\r
-// The next 3 are all non-cached, sequential & non-speculative\r
-//\r
-#define MA_UC 0x4 // Non-coalescing, sequential & non-speculative\r
-#define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative\r
-// & fetchadd exported\r
-//\r
-#define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.\r
-#define MA_NAT 0xf // NaT page\r
-//\r
-// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the\r
-// base of IVA (Interruption Vector Address)\r
-//\r
-#define IVT_SIZE 0x8000\r
-#define EXTRA_ALIGNMENT 0x1000\r
-\r
-#define OFF_VHPTFLT 0x0000 // VHPT Translation fault\r
-#define OFF_ITLBFLT 0x0400 // Instruction TLB fault\r
-#define OFF_DTLBFLT 0x0800 // Data TLB fault\r
-#define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault\r
-#define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault\r
-#define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault\r
-#define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault\r
-#define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault\r
-#define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault\r
-#define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault\r
-#define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault\r
-#define OFF_BREAKFLT 0x2C00 // Break Inst fault\r
-#define OFF_EXTINT 0x3000 // External Interrupt\r
-//\r
-// Offset 0x3400 to 0x0x4C00 are reserved\r
-//\r
-#define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault\r
-#define OFF_KEYPERMFLT 0x5100 // Key Permission fault\r
-#define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt\r
-#define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault\r
-#define OFF_GPFLT 0x5400 // General Exception fault\r
-#define OFF_FPDISFLT 0x5500 // Disable-FP fault\r
-#define OFF_NATFLT 0x5600 // NAT Consumption fault\r
-#define OFF_SPECLNFLT 0x5700 // Speculation fault\r
-#define OFF_DBGFLT 0x5900 // Debug fault\r
-#define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault\r
-#define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault\r
-#define OFF_FPFLT 0x5C00 // Floating Point fault\r
-#define OFF_FPTRAP 0x5D00 // Floating Point Trap\r
-#define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap\r
-#define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap\r
-#define OFF_SSTEPTRAP 0x6000 // Single Step Trap\r
-//\r
-// Offset 0x6100 to 0x6800 are reserved\r
-//\r
-#define OFF_IA32EXCEPTN 0x6900 // iA32 Exception\r
-#define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept\r
-#define OFF_IA32INT 0x6B00 // iA32 Interrupt\r
-#define NUMBER_OF_VECTORS 0x100\r
-//\r
-// Privilege levels\r
-//\r
-#define PL_KERNEL 0\r
-#define PL_USER 3\r
-\r
-//\r
-// Instruction set (IS) bits\r
-//\r
-#define IS_IA64 0\r
-#define IS_IA 1\r
-\r
-//\r
-// RSC while in kernel: enabled, little endian, PL = 0, eager mode\r
-//\r
-#define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r
-\r
-//\r
-// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode\r
-//\r
-#define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r
-\r
-//\r
-// RSE disabled: disabled, PL = 0, little endian, eager mode\r
-//\r
-#define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r
-\r
-#define NAT_BITS_PER_RNAT_REG 63\r
-\r
-//\r
-// Macros for generating PTE0 and PTE1 value\r
-//\r
-#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \\r
- ( ( ed << PTE0_ED ) | \\r
- ( ppn12_47 << PTE0_PPN ) | \\r
- ( ar << PTE0_AR ) | \\r
- ( pl << PTE0_PL ) | \\r
- ( d << PTE0_D ) | \\r
- ( a << PTE0_A ) | \\r
- ( ma << PTE0_MA ) | \\r
- ( p << PTE0_P ) \\r
- )\r
-\r
-#define ITIR(ppn48_63, key, ps) \\r
- ( ( ps << ITIR_PS ) | \\r
- ( key << ITIR_KEY ) | \\r
- ( ppn48_63 << ITIR_PPN ) \\r
- )\r
-\r
-//\r
-// Macro to generate mask value from bit position. The result is a\r
-// 64-bit.\r
-//\r
-#define BITMASK(bp, value) (value << bp)\r
-\r
-#define BUNDLE_SIZE 16\r
-#define SPURIOUS_INT 0xF\r
-\r
-#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;\r
-\r
-#define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;\r
-\r
-#endif\r
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