/** @file\r
Supporting functions implementaion for PCI devices management.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
0,\r
&Supports\r
);\r
- Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
+ //\r
+ // By default every bridge's IO and MMIO spaces are enabled.\r
+ // Bridge's Bus Master will be enabled when any device behind it requests\r
+ // to enable Bus Master.\r
+ //\r
+ Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);\r
PciIoDevice->PciIo.Attributes (\r
&(PciIoDevice->PciIo),\r
EfiPciIoAttributeOperationEnable,\r
0,\r
&Supports\r
);\r
- Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
+ //\r
+ // By default every bridge's IO and MMIO spaces are enabled.\r
+ // Bridge's Bus Master will be enabled when any device behind it requests\r
+ // to enable Bus Master.\r
+ //\r
+ Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);\r
PciIoDevice->PciIo.Attributes (\r
&(PciIoDevice->PciIo),\r
EfiPciIoAttributeOperationEnable,\r
return Status;\r
}\r
//\r
- // Assume the PCI Root Bridge supports DAC\r
+ // Assume the PCI Root Bridge supports DAC and Bus Master.\r
//\r
PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE |\r
+ EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);\r
\r
} else {\r
\r
//\r
Command = EFI_PCI_COMMAND_IO_SPACE |\r
EFI_PCI_COMMAND_MEMORY_SPACE |\r
- EFI_PCI_COMMAND_BUS_MASTER |\r
EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
\r
+ //\r
+ // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.\r
+ // So only test the Bus Master capability for PCI devices.\r
+ //\r
+ if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) {\r
+ Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
+ }\r
+\r
BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16;\r
\r
//\r
\r
//\r
// Set the supported attributes for specified PCI device\r
+ // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.\r
//\r
+ if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) {\r
+ Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
+ }\r
PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SUPPORTS);\r
\r
//\r
//\r
Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE |\r
+ EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);\r
\r
//\r
// Record the new attribute of the Root Bridge\r
}\r
//\r
// The upstream bridge should be also set to revelant attribute\r
- // expect for IO, Mem and BusMaster\r
+ // expect for IO and Mem\r
//\r
UpStreamAttributes = Attributes &\r
(~(EFI_PCI_IO_ATTRIBUTE_IO |\r
- EFI_PCI_IO_ATTRIBUTE_MEMORY |\r
- EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r
+ EFI_PCI_IO_ATTRIBUTE_MEMORY\r
)\r
);\r
UpStreamBridge = PciIoDevice->Parent;\r