--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials are licensed and made available\r
+* under the terms and conditions of the BSD License which accompanies this\r
+* distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+ VOID\r
+ )\r
+{\r
+ // Ideally we would like to use the GICC IIDR Architecture version here, but\r
+ // this does not seem to be very reliable as the implementation could easily\r
+ // get it wrong. It is more reliable to check if the GICv3 System Register\r
+ // feature is implemented on the CPU. This is also convenient as our GICv3\r
+ // driver requires SRE. If only Memory mapped access is available we try to\r
+ // drive the GIC as a v2.\r
+ if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {\r
+ return ARM_GIC_ARCH_REVISION_3;\r
+ }\r
+\r
+ return ARM_GIC_ARCH_REVISION_2;\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials are licensed and made available\r
+* under the terms and conditions of the BSD License which accompanies this\r
+* distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+ VOID\r
+ )\r
+{\r
+ // Ideally we would like to use the GICC IIDR Architecture version here, but\r
+ // this does not seem to be very reliable as the implementation could easily\r
+ // get it wrong. It is more reliable to check if the GICv3 System Register\r
+ // feature is implemented on the CPU. This is also convenient as our GICv3\r
+ // driver requires SRE. If only Memory mapped access is available we try to\r
+ // drive the GIC as a v2.\r
+ if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {\r
+ return ARM_GIC_ARCH_REVISION_3;\r
+ }\r
+\r
+ return ARM_GIC_ARCH_REVISION_2;\r
+}\r
\r
#include "GicV2/ArmGicV2Lib.h"\r
\r
-ARM_GIC_ARCH_REVISION\r
-EFIAPI\r
-ArmGicGetSupportedArchRevision (\r
- VOID\r
- )\r
-{\r
- return ARM_GIC_ARCH_REVISION_2;\r
-}\r
-\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
GicV2/ArmGicV2Lib.c\r
GicV2/ArmGicV2NonSecLib.c\r
\r
+[Sources.ARM]\r
+ Arm/ArmGicArchLib.c\r
+\r
+[Sources.AARCH64]\r
+ AArch64/ArmGicArchLib.c\r
+\r
[LibraryClasses]\r
+ ArmLib\r
DebugLib\r
IoLib\r
\r
GicV2/ArmGicV2Lib.c\r
GicV2/ArmGicV2SecLib.c\r
\r
+[Sources.ARM]\r
+ Arm/ArmGicArchLib.c\r
+\r
+[Sources.AARCH64]\r
+ AArch64/ArmGicArchLib.c\r
+\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
\r
[LibraryClasses]\r
ArmLib\r
- ArmPlatformLib\r
DebugLib\r
IoLib\r
- PcdLib\r
// GIC definitions\r
//\r
typedef enum {\r
- ARM_GIC_ARCH_REVISION_2\r
+ ARM_GIC_ARCH_REVISION_2,\r
+ ARM_GIC_ARCH_REVISION_3\r
} ARM_GIC_ARCH_REVISION;\r
\r
//\r