]> git.proxmox.com Git - mirror_edk2.git/commitdiff
UefiCpuPkg/MpInitLib: Add CPU_VOLATILE_REGISTERS & worker functions
authorJeff Fan <jeff.fan@intel.com>
Wed, 20 Jul 2016 15:47:59 +0000 (23:47 +0800)
committerJeff Fan <jeff.fan@intel.com>
Wed, 17 Aug 2016 12:00:19 +0000 (20:00 +0800)
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored
after APs received INIT IPI.

Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to
save/restore CRx and DRx. It also check if Debugging Extensions supported or
not.

v5:
  1. Add comment block for structure CPU_VOLATILE_REGISTERS.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
UefiCpuPkg/Library/MpInitLib/MpLib.c
UefiCpuPkg/Library/MpInitLib/MpLib.h

index 70e5eb1b411a843eb6369819ee350531dffbb258..0832228d71cab1216e548eabbd208c2ac6c6bdd6 100644 (file)
@@ -46,6 +46,73 @@ SetApState (
   ReleaseSpinLock (&CpuData->ApLock);\r
 }\r
 \r
+/**\r
+  Save the volatile registers required to be restored following INIT IPI.\r
+\r
+  @param[out]  VolatileRegisters    Returns buffer saved the volatile resisters\r
+**/\r
+VOID\r
+SaveVolatileRegisters (\r
+  OUT CPU_VOLATILE_REGISTERS    *VolatileRegisters\r
+  )\r
+{\r
+  CPUID_VERSION_INFO_EDX        VersionInfoEdx;\r
+\r
+  VolatileRegisters->Cr0 = AsmReadCr0 ();\r
+  VolatileRegisters->Cr3 = AsmReadCr3 ();\r
+  VolatileRegisters->Cr4 = AsmReadCr4 ();\r
+\r
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+  if (VersionInfoEdx.Bits.DE != 0) {\r
+    //\r
+    // If processor supports Debugging Extensions feature\r
+    // by CPUID.[EAX=01H]:EDX.BIT2\r
+    //\r
+    VolatileRegisters->Dr0 = AsmReadDr0 ();\r
+    VolatileRegisters->Dr1 = AsmReadDr1 ();\r
+    VolatileRegisters->Dr2 = AsmReadDr2 ();\r
+    VolatileRegisters->Dr3 = AsmReadDr3 ();\r
+    VolatileRegisters->Dr6 = AsmReadDr6 ();\r
+    VolatileRegisters->Dr7 = AsmReadDr7 ();\r
+  }\r
+}\r
+\r
+/**\r
+  Restore the volatile registers following INIT IPI.\r
+\r
+  @param[in]  VolatileRegisters   Pointer to volatile resisters\r
+  @param[in]  IsRestoreDr         TRUE:  Restore DRx if supported\r
+                                  FALSE: Do not restore DRx\r
+**/\r
+VOID\r
+RestoreVolatileRegisters (\r
+  IN CPU_VOLATILE_REGISTERS    *VolatileRegisters,\r
+  IN BOOLEAN                   IsRestoreDr\r
+  )\r
+{\r
+  CPUID_VERSION_INFO_EDX        VersionInfoEdx;\r
+\r
+  AsmWriteCr0 (VolatileRegisters->Cr0);\r
+  AsmWriteCr3 (VolatileRegisters->Cr3);\r
+  AsmWriteCr4 (VolatileRegisters->Cr4);\r
+\r
+  if (IsRestoreDr) {\r
+    AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+    if (VersionInfoEdx.Bits.DE != 0) {\r
+      //\r
+      // If processor supports Debugging Extensions feature\r
+      // by CPUID.[EAX=01H]:EDX.BIT2\r
+      //\r
+      AsmWriteDr0 (VolatileRegisters->Dr0);\r
+      AsmWriteDr1 (VolatileRegisters->Dr1);\r
+      AsmWriteDr2 (VolatileRegisters->Dr2);\r
+      AsmWriteDr3 (VolatileRegisters->Dr3);\r
+      AsmWriteDr6 (VolatileRegisters->Dr6);\r
+      AsmWriteDr7 (VolatileRegisters->Dr7);\r
+    }\r
+  }\r
+}\r
+\r
 /**\r
   Detect whether Mwait-monitor feature is supported.\r
 \r
@@ -204,6 +271,10 @@ MpInitLibInitialize (
   CpuMpData->CpuInfoInHob     = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber);\r
   InitializeSpinLock(&CpuMpData->MpLock);\r
   //\r
+  // Save BSP's Control registers to APs\r
+  //\r
+  SaveVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters);\r
+  //\r
   // Set BSP basic information\r
   //\r
   InitializeApData (CpuMpData, 0, 0);\r
index 84bd8721982caf6b55206cfd1ebaa9651b5d62d5..ca8bd445ba668d993c075a1dbada68d1e2617c0e 100644 (file)
@@ -65,6 +65,21 @@ typedef enum {
   CpuStateDisabled\r
 } CPU_STATE;\r
 \r
+//\r
+// CPU volatile registers around INIT-SIPI-SIPI\r
+//\r
+typedef struct {\r
+  UINTN                          Cr0;\r
+  UINTN                          Cr3;\r
+  UINTN                          Cr4;\r
+  UINTN                          Dr0;\r
+  UINTN                          Dr1;\r
+  UINTN                          Dr2;\r
+  UINTN                          Dr3;\r
+  UINTN                          Dr6;\r
+  UINTN                          Dr7;\r
+} CPU_VOLATILE_REGISTERS;\r
+\r
 //\r
 // AP related data\r
 //\r
@@ -78,6 +93,7 @@ typedef struct {
   UINT32                         Health;\r
   BOOLEAN                        CpuHealthy;\r
   volatile CPU_STATE             State;\r
+  CPU_VOLATILE_REGISTERS         VolatileRegisters;\r
   BOOLEAN                        Waiting;\r
   BOOLEAN                        *Finished;\r
   UINT64                         ExpectedTime;\r