]> git.proxmox.com Git - mirror_edk2.git/commitdiff
IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
authorTed Kuo <ted.kuo@intel.com>
Fri, 15 Apr 2022 08:37:40 +0000 (01:37 -0700)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Sat, 16 Apr 2022 00:18:14 +0000 (00:18 +0000)
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added SecFspSecPlatformLibNull support for X64.
2.Added X64 support to IntelFsp2Pkg.dsc.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
IntelFsp2Pkg/IntelFsp2Pkg.dsc
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm [new file with mode: 0644]
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm [new file with mode: 0644]

index c1414f7e75b8a2bad9e7c62930898163b09ac8e3..7cf7e88245405c7923ce72678d01ffedf1dd9a06 100644 (file)
@@ -1,7 +1,7 @@
 ## @file\r
 # Provides driver and definitions to build fsp.\r
 #\r
-# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
 # SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
 ##\r
@@ -12,7 +12,7 @@
   PLATFORM_VERSION               = 0.1\r
   DSC_SPECIFICATION              = 0x00010005\r
   OUTPUT_DIRECTORY               = Build/IntelFsp2Pkg\r
-  SUPPORTED_ARCHITECTURES        = IA32\r
+  SUPPORTED_ARCHITECTURES        = IA32|X64\r
   BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT\r
   SKUID_IDENTIFIER               = DEFAULT\r
 \r
index 42e7d83c3297b88424fb2f4e543edd082ab410af..55ee1b98a2ab67539be22f2fd4311b2fd2b8dd8a 100644 (file)
@@ -1,7 +1,7 @@
 ## @file\r
 #  NULL instance of Platform Sec Lib.\r
 #\r
-#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
 #\r
 #  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -23,7 +23,7 @@
 #\r
 # The following information is for reference only and not required by the build tools.\r
 #\r
-#  VALID_ARCHITECTURES           = IA32\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
 #\r
 \r
 ################################################################################\r
   Ia32/Flat32.nasm\r
   Ia32/SecCarInit.nasm\r
 \r
+[Sources.X64]\r
+  X64/Long64.nasm\r
+  X64/SecCarInit.nasm\r
+\r
 ################################################################################\r
 #\r
 # Package Dependency Section - list of Package files that are required for\r
diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm
new file mode 100644 (file)
index 0000000..836257f
--- /dev/null
@@ -0,0 +1,31 @@
+;; @file\r
+;  This is the code that performs early platform initialization.\r
+;  It consumes the reset vector, configures the stack.\r
+;\r
+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;;\r
+\r
+;\r
+; Define assembler characteristics\r
+;\r
+\r
+extern   ASM_PFX(TempRamInitApi)\r
+\r
+SECTION .text\r
+\r
+%macro RET_RSI  0\r
+\r
+  movd    rsi, mm7                      ; restore RSI from MM7\r
+  jmp     rsi\r
+\r
+%endmacro\r
+\r
+;\r
+; Perform early platform initialization\r
+;\r
+global ASM_PFX(SecPlatformInit)\r
+ASM_PFX(SecPlatformInit):\r
+\r
+  RET_RSI\r
+\r
diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm
new file mode 100644 (file)
index 0000000..e64c77e
--- /dev/null
@@ -0,0 +1,40 @@
+;; @file\r
+;  SEC CAR function\r
+;\r
+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;;\r
+\r
+;\r
+; Define assembler characteristics\r
+;\r
+\r
+%macro RET_RSI 0\r
+\r
+  movd    rsi, mm7                      ; move ReturnAddress from MM7 to RSI\r
+  jmp     rsi\r
+\r
+%endmacro\r
+\r
+SECTION .text\r
+\r
+;-----------------------------------------------------------------------------\r
+;\r
+;  Section:     SecCarInit\r
+;\r
+;  Description: This function initializes the Cache for Data, Stack, and Code\r
+;\r
+;-----------------------------------------------------------------------------\r
+global ASM_PFX(SecCarInit)\r
+ASM_PFX(SecCarInit):\r
+\r
+  ;\r
+  ; Set up CAR\r
+  ;\r
+\r
+  xor    rax, rax\r
+\r
+SecCarInitExit:\r
+\r
+  RET_RSI\r
+\r