--- /dev/null
+\r
+#include "BaseLibInternals.h"\r
+\r
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Thunk.asm\r
+;\r
+; Abstract:\r
+;\r
+; Real mode thunk\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+global ASM_PFX(m16Size)\r
+global ASM_PFX(mThunk16Attr)\r
+global ASM_PFX(m16Gdt)\r
+global ASM_PFX(m16GdtrBase)\r
+global ASM_PFX(mTransition)\r
+global ASM_PFX(m16Start)\r
+\r
+struc IA32_REGS\r
+\r
+ ._EDI: resd 1\r
+ ._ESI: resd 1\r
+ ._EBP: resd 1\r
+ ._ESP: resd 1\r
+ ._EBX: resd 1\r
+ ._EDX: resd 1\r
+ ._ECX: resd 1\r
+ ._EAX: resd 1\r
+ ._DS: resw 1\r
+ ._ES: resw 1\r
+ ._FS: resw 1\r
+ ._GS: resw 1\r
+ ._EFLAGS: resd 1\r
+ ._EIP: resd 1\r
+ ._CS: resw 1\r
+ ._SS: resw 1\r
+ .size:\r
+\r
+endstruc\r
+\r
+;; .const\r
+\r
+SECTION .data\r
+\r
+;\r
+; These are global constant to convey information to C code.\r
+;\r
+ASM_PFX(m16Size) DW InternalAsmThunk16 - ASM_PFX(m16Start)\r
+ASM_PFX(mThunk16Attr) DW _ThunkAttr - ASM_PFX(m16Start)\r
+ASM_PFX(m16Gdt) DW _NullSegDesc - ASM_PFX(m16Start)\r
+ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)\r
+ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)\r
+\r
+SECTION .text\r
+\r
+ASM_PFX(m16Start):\r
+\r
+SavedGdt:\r
+ dw 0\r
+ dd 0\r
+\r
+;------------------------------------------------------------------------------\r
+; _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
+; by user code. It will be shadowed to somewhere in memory below 1MB.\r
+;------------------------------------------------------------------------------\r
+_BackFromUserCode:\r
+ ;\r
+ ; The order of saved registers on the stack matches the order they appears\r
+ ; in IA32_REGS structure. This facilitates wrapper function to extract them\r
+ ; into that structure.\r
+ ;\r
+ push ss\r
+ push cs\r
+ DB 66h\r
+ call @Base ; push eip\r
+@Base:\r
+ pushfw ; pushfd actually\r
+ cli ; disable interrupts\r
+ push gs\r
+ push fs\r
+ push es\r
+ push ds\r
+ pushaw ; pushad actually\r
+ DB 66h, 0bah ; mov edx, imm32\r
+_ThunkAttr: dd 0\r
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15\r
+ jz @1\r
+ mov eax, 15cd2401h ; mov ax, 2401h & int 15h\r
+ cli ; disable interrupts\r
+ jnc @2\r
+@1:\r
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL\r
+ jz @2\r
+ in al, 92h\r
+ or al, 2\r
+ out 92h, al ; deactivate A20M#\r
+@2:\r
+ xor ax, ax ; xor eax, eax\r
+ mov eax, ss ; mov ax, ss\r
+ DB 67h\r
+ lea bp, [esp + IA32_REGS.size]\r
+ ;\r
+ ; esi's in the following 2 instructions are indeed bp in 16-bit code. Fact\r
+ ; is "esi" in 32-bit addressing mode has the same encoding of "bp" in 16-\r
+ ; bit addressing mode.\r
+ ;\r
+ mov [esi - IA32_REGS.size + IA32_REGS._ESP], bp\r
+ mov ebx, [esi - IA32_REGS.size + IA32_REGS._EIP]\r
+ shl ax, 4 ; shl eax, 4\r
+ add bp, ax ; add ebp, eax\r
+ DB 66h, 0b8h ; mov eax, imm32\r
+SavedCr4: DD 0\r
+ mov cr4, eax\r
+ DB 66h\r
+ lgdt [cs:edi + (SavedGdt - @Base)]\r
+ DB 66h, 0b8h ; mov eax, imm32\r
+SavedCr0: DD 0\r
+ mov cr0, eax\r
+ DB 0b8h ; mov ax, imm16\r
+SavedSs DW 0\r
+ mov ss, eax\r
+ DB 66h, 0bch ; mov esp, imm32\r
+SavedEsp DD 0\r
+ DB 66h\r
+ retf ; return to protected mode\r
+\r
+_EntryPoint:\r
+ DD _ToUserCode - ASM_PFX(m16Start)\r
+ DW 8h\r
+_16Idtr:\r
+ DW (1 << 10) - 1\r
+ DD 0\r
+_16Gdtr:\r
+ DW GdtEnd - _NullSegDesc - 1\r
+_16GdtrBase:\r
+ DD _NullSegDesc\r
+\r
+;------------------------------------------------------------------------------\r
+; _ToUserCode() takes control in real mode before passing control to user code.\r
+; It will be shadowed to somewhere in memory below 1MB.\r
+;------------------------------------------------------------------------------\r
+_ToUserCode:\r
+ mov edx, ss\r
+ mov ss, ecx ; set new segment selectors\r
+ mov ds, ecx\r
+ mov es, ecx\r
+ mov fs, ecx\r
+ mov gs, ecx\r
+ mov cr0, eax ; real mode starts at next instruction\r
+ ; which (per SDM) *must* be a far JMP.\r
+ DB 0eah\r
+_RealAddr: DW 0, 0\r
+\r
+ mov cr4, ebp\r
+ mov ss, esi ; set up 16-bit stack segment\r
+ xchg sp, bx ; set up 16-bit stack pointer\r
+\r
+; mov bp, [esp + sizeof(IA32_REGS)\r
+ DB 67h\r
+ mov ebp, [esp + IA32_REGS.size] ; BackFromUserCode address from stack\r
+\r
+; mov cs:[bp + (SavedSs - _BackFromUserCode)], dx\r
+ mov [cs:esi + (SavedSs - _BackFromUserCode)], edx\r
+\r
+; mov cs:[bp + (SavedEsp - _BackFromUserCode)], ebx\r
+ DB 2eh, 66h, 89h, 9eh\r
+ DW SavedEsp - _BackFromUserCode\r
+\r
+; lidt cs:[bp + (_16Idtr - _BackFromUserCode)]\r
+ DB 2eh, 66h, 0fh, 01h, 9eh\r
+ DW _16Idtr - _BackFromUserCode\r
+\r
+ popaw ; popad actually\r
+ pop ds\r
+ pop es\r
+ pop fs\r
+ pop gs\r
+ popfw ; popfd\r
+\r
+ DB 66h ; Use 32-bit addressing for "retf" below\r
+ retf ; transfer control to user code\r
+\r
+ALIGN 16\r
+_NullSegDesc DQ 0\r
+_16CsDesc:\r
+ DW -1\r
+ DW 0\r
+ DB 0\r
+ DB 9bh\r
+ DB 8fh ; 16-bit segment, 4GB limit\r
+ DB 0\r
+_16DsDesc:\r
+ DW -1\r
+ DW 0\r
+ DB 0\r
+ DB 93h\r
+ DB 8fh ; 16-bit segment, 4GB limit\r
+ DB 0\r
+GdtEnd:\r
+\r
+;------------------------------------------------------------------------------\r
+; IA32_REGISTER_SET *\r
+; EFIAPI\r
+; InternalAsmThunk16 (\r
+; IN IA32_REGISTER_SET *RegisterSet,\r
+; IN OUT VOID *Transition\r
+; );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(InternalAsmThunk16)\r
+ASM_PFX(InternalAsmThunk16):\r
+ push ebp\r
+ push ebx\r
+ push esi\r
+ push edi\r
+ push ds\r
+ push es\r
+ push fs\r
+ push gs\r
+ mov esi, [esp + 36] ; esi <- RegSet, the 1st parameter\r
+ movzx edx, word [esi + IA32_REGS._SS]\r
+ mov edi, [esi + IA32_REGS._ESP]\r
+ add edi, - (IA32_REGS.size + 4) ; reserve stack space\r
+ mov ebx, edi ; ebx <- stack offset\r
+ imul eax, edx, 16 ; eax <- edx * 16\r
+ push IA32_REGS.size / 4\r
+ add edi, eax ; edi <- linear address of 16-bit stack\r
+ pop ecx\r
+ rep movsd ; copy RegSet\r
+ mov eax, [esp + 40] ; eax <- address of transition code\r
+ mov esi, edx ; esi <- 16-bit stack segment\r
+ lea edx, [eax + (SavedCr0 - ASM_PFX(m16Start))]\r
+ mov ecx, eax\r
+ and ecx, 0fh\r
+ shl eax, 12\r
+ lea ecx, [ecx + (_BackFromUserCode - ASM_PFX(m16Start))]\r
+ mov ax, cx\r
+ stosd ; [edi] <- return address of user code\r
+ add eax, _RealAddr + 4 - _BackFromUserCode\r
+ mov [edx + (_RealAddr - SavedCr0)], eax\r
+ sgdt [edx + (SavedGdt - SavedCr0)]\r
+ sidt [esp + 36] ; save IDT stack in argument space\r
+ mov eax, cr0\r
+ mov [edx], eax ; save CR0 in SavedCr0\r
+ and eax, 7ffffffeh ; clear PE, PG bits\r
+ mov ebp, cr4\r
+ mov [edx + (SavedCr4 - SavedCr0)], ebp\r
+ and ebp, ~30h ; clear PAE, PSE bits\r
+ push 10h\r
+ pop ecx ; ecx <- selector for data segments\r
+ lgdt [edx + (_16Gdtr - SavedCr0)]\r
+ pushfd ; Save df/if indeed\r
+ call dword far [edx + (_EntryPoint - SavedCr0)]\r
+ popfd\r
+ lidt [esp + 36] ; restore protected mode IDTR\r
+ lea eax, [ebp - IA32_REGS.size] ; eax <- the address of IA32_REGS\r
+ pop gs\r
+ pop fs\r
+ pop es\r
+ pop ds\r
+ pop edi\r
+ pop esi\r
+ pop ebx\r
+ pop ebp\r
+ ret\r
projects / mirror_edk2.git / commitdiff