/** @file\r
* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- //Clean Data cache\r
- ArmCleanInvalidateDataCache ();\r
-\r
- //Invalidate instruction cache\r
+ // Data Cache enabled on Primary core when MMU is enabled.\r
+ ArmDisableDataCache ();\r
+ // Invalidate Data cache\r
+ ArmInvalidateDataCache ();\r
+ // Invalidate instruction cache\r
ArmInvalidateInstructionCache ();\r
-\r
- // Enable Instruction & Data caches\r
- ArmEnableDataCache ();\r
+ // Enable Instruction Caches on all cores.\r
ArmEnableInstructionCache ();\r
\r
//\r
/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
StartTimeStamp = 0;\r
}\r
\r
- // Clean Data cache\r
- ArmCleanInvalidateDataCache ();\r
-\r
+ // Data Cache enabled on Primary core when MMU is enabled.\r
+ ArmDisableDataCache ();\r
+ // Invalidate Data cache\r
+ ArmInvalidateDataCache ();\r
// Invalidate instruction cache\r
ArmInvalidateInstructionCache ();\r
-\r
- //TODO:Drain Write Buffer\r
-\r
- // Enable Instruction & Data caches\r
- ArmEnableDataCache ();\r
+ // Enable Instruction Caches on all cores.\r
ArmEnableInstructionCache ();\r
\r
// Define the Global Variable region when we are not running in XIP\r