MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging

5-level paging is documented in white paper:
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf

Commit f8113e25001e715390127f23e2197252cbd6d1a2
changed Cpuid.h already.

This patch updates IA32_CR4 structure to include LA57 field.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
(cherry picked from commit 7c5010c7f88b790f4524c4a5311819e3af5e2752)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index ebd7dd274cf4387eb50fdd6b59d53a556dd51042..a22bfc9fadff9b0494b930f7a6e9f30152153ac9 100644 (file)
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -5324,7 +5324,8 @@ typedef union {
     UINT32  OSXMMEXCPT:1;   ///< Operating System Support for\r
                             ///< Unmasked SIMD Floating Point\r
                             ///< Exceptions.\r
-    UINT32  Reserved_0:2;   ///< Reserved.\r
+    UINT32  Reserved_2:1;   ///< Reserved.\r
+    UINT32  LA57:1;         ///< Linear Address 57bit.\r
     UINT32  VMXE:1;         ///< VMX Enable\r
     UINT32  Reserved_1:18;  ///< Reserved.\r
   } Bits;\r