ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contents

Peculiarly enough, the current page table manipulation code takes it
upon itself to write back and invalidate the memory contents covered
by page and section mappings when their memory attributes change. It
is not generally the case that data must be written back when such a
change occurs, even when switching from cacheable to non-cacheable
attributes, and in some cases, it is actually causing problems. (The
cache maintenance is also performed on the PCIe MMIO regions as they
get mapped by the PCI bus driver, and under virtualization, each
cache maintenance operation on an emulated MMIO region triggers a
round trip to the host and back)

So let's just drop this code.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
index 774a7ccf59c0f92f81fa4e8ff202aac815ae589e..9eb6dd8d25c844d084b534c6dd9a2936d3c66c1f 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
@@ -597,12 +597,6 @@ UpdatePageEntries (
     if (CurrentPageTableEntry  != PageTableEntry) {\r
       Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r
 \r
-      // Clean/invalidate the cache for this page, but only\r
-      // if we are modifying the memory type attributes\r
-      if (((CurrentPageTableEntry ^ PageTableEntry) & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) != 0) {\r
-        WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r
-      }\r
-\r
       // Only need to update if we are changing the entry\r
       PageTable[PageTableIndex] = PageTableEntry;\r
       ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
@@ -718,12 +712,6 @@ UpdateSectionEntries (
       if (CurrentDescriptor  != Descriptor) {\r
         Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r
 \r
-        // Clean/invalidate the cache for this section, but only\r
-        // if we are modifying the memory type attributes\r
-        if (((CurrentDescriptor ^ Descriptor) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) != 0) {\r
-          WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
-        }\r
-\r
         // Only need to update if we are changing the descriptor\r
         FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
         ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r