BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
Add RISC-V architecture on RISC-V EDK2 CI.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
# Azure Pipeline build file for a build using ubuntu and GCC5\r
#\r
# Copyright (c) Microsoft Corporation.\r
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
##\r
trigger:\r
parameters:\r
tool_chain_tag: 'GCC5'\r
vm_image: 'ubuntu-latest'\r
- arch_list: "IA32,X64,ARM,AARCH64"\r
+ arch_list: "IA32,X64,ARM,AARCH64,RISCV64"\r
\r