#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGenericTimerCounterLib.h>\r
-#include <Library/ArmArchTimer.h>\r
\r
#include <Protocol/Timer.h>\r
#include <Protocol/HardwareInterrupt.h>\r
#define __AARCH64_H__\r
\r
#include <Chipset/AArch64Mmu.h>\r
-#include <Chipset/ArmArchTimer.h>\r
\r
// ARM Interrupt ID in Exception Table\r
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __ARM_ARCH_TIMER_H_\r
-#define __ARM_ARCH_TIMER_H_\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadCntFrq (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntFrq (\r
- UINTN FreqInHz\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-ArmReadCntPct (\r
- VOID\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadCntkCtl (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntkCtl (\r
- UINTN Val\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadCntpTval (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntpTval (\r
- UINTN Val\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadCntpCtl (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntpCtl (\r
- UINTN Val\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadCntvTval (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntvTval (\r
- UINTN Val\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadCntvCtl (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntvCtl (\r
- UINTN Val\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-ArmReadCntvCt (\r
- VOID\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-ArmReadCntpCval (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntpCval (\r
- UINT64 Val\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-ArmReadCntvCval (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntvCval (\r
- UINT64 Val\r
- );\r
-\r
-UINT64\r
-EFIAPI\r
-ArmReadCntvOff (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCntvOff (\r
- UINT64 Val\r
- );\r
-\r
-#endif // __ARM_ARCH_TIMER_H_\r
-\r
#define __ARM_V7_H__\r
\r
#include <Chipset/ArmV7Mmu.h>\r
-#include <Chipset/ArmArchTimer.h>\r
\r
// ARM Interrupt ID in Exception Table\r
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __ARM_ARCH_TIMER_H__\r
-#define __ARM_ARCH_TIMER_H__\r
-\r
-#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
-#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
-#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
-\r
-typedef enum {\r
- CntFrq = 0,\r
- CntPct,\r
- CntkCtl,\r
- CntpTval,\r
- CntpCtl,\r
- CntvTval,\r
- CntvCtl,\r
- CntvCt,\r
- CntpCval,\r
- CntvCval,\r
- CntvOff,\r
- CnthCtl,\r
- CnthpTval,\r
- CnthpCtl,\r
- CnthpCval,\r
- RegMaximum\r
-} ARM_ARCH_TIMER_REGS;\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerReadReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- OUT VOID *DstBuf\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerWriteReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- IN VOID *SrcBuf\r
- );\r
-\r
-#endif // __ARM_ARCH_TIMER_H__\r
IN UINTN Bits\r
);\r
\r
+//\r
+// Accessors for the architected generic timer registers\r
+//\r
+\r
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntFrq (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntFrq (\r
+ UINTN FreqInHz\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntPct (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntkCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntkCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpTval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpTval (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvTval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvTval (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCt (\r
+ VOID\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntpCval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCval (\r
+ UINT64 Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCval (\r
+ UINT64 Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvOff (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvOff (\r
+ UINT64 Val\r
+ );\r
+\r
#endif // __ARM_LIB__\r
**/\r
\r
#include <Library/ArmGenericTimerCounterLib.h>\r
-#include <Library/ArmArchTimer.h>\r
+#include <Library/ArmLib.h>\r
\r
VOID\r
EFIAPI\r
{\r
UINTN TimerCtrlReg;\r
\r
- ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
+ TimerCtrlReg = ArmReadCntpCtl ();\r
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r
- ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
+ ArmWriteCntpCtl (TimerCtrlReg);\r
}\r
\r
VOID\r
{\r
UINTN TimerCtrlReg;\r
\r
- ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
+ TimerCtrlReg = ArmReadCntpCtl ();\r
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r
- ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
+ ArmWriteCntpCtl (TimerCtrlReg);\r
}\r
\r
VOID\r
IN UINTN FreqInHz\r
)\r
{\r
- ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);\r
+ ArmWriteCntFrq (FreqInHz);\r
}\r
\r
UINTN\r
VOID\r
)\r
{\r
- UINTN ArchTimerFreq = 0;\r
- ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);\r
- return ArchTimerFreq;\r
+ return ArmReadCntFrq ();\r
}\r
\r
UINTN\r
VOID\r
)\r
{\r
- UINTN ArchTimerValue;\r
- ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerValue);\r
-\r
- return ArchTimerValue;\r
+ return ArmReadCntpTval ();\r
}\r
\r
\r
IN UINTN Value\r
)\r
{\r
- ArmArchTimerWriteReg (CntpTval, (VOID *)&Value);\r
+ ArmWriteCntpTval (Value);\r
}\r
\r
UINT64\r
VOID\r
)\r
{\r
- UINT64 SystemCount;\r
- ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);\r
-\r
- return SystemCount;\r
+ return ArmReadCntPct ();\r
}\r
\r
UINTN\r
VOID\r
)\r
{\r
- UINTN Value;\r
- ArmArchTimerReadReg (CntpCtl, (VOID *)&Value);\r
-\r
- return Value;\r
+ return ArmReadCntpCtl ();\r
}\r
\r
VOID\r
UINTN Value\r
)\r
{\r
- ArmArchTimerWriteReg (CntpCtl, (VOID *)&Value);\r
+ ArmWriteCntpCtl (Value);\r
}\r
\r
UINT64\r
VOID\r
)\r
{\r
- UINT64 Value;\r
- ArmArchTimerReadReg (CntpCval, (VOID *)&Value);\r
-\r
- return Value;\r
+ return ArmReadCntpCval ();\r
}\r
\r
VOID\r
IN UINT64 Value\r
)\r
{\r
- ArmArchTimerWriteReg (CntpCval, (VOID *)&Value);\r
+ ArmWriteCntpCval (Value);\r
}\r
**/\r
\r
#include <Library/ArmGenericTimerCounterLib.h>\r
-#include <Library/ArmArchTimer.h>\r
+#include <Library/ArmLib.h>\r
\r
VOID\r
EFIAPI\r
{\r
UINTN TimerCtrlReg;\r
\r
- ArmArchTimerReadReg (CntvCtl, (VOID *)&TimerCtrlReg);\r
+ TimerCtrlReg = ArmReadCntvCtl ();\r
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r
\r
//\r
// leaving this in once KVM gets fixed.\r
//\r
TimerCtrlReg &= ~ARM_ARCH_TIMER_IMASK;\r
- ArmArchTimerWriteReg (CntvCtl, (VOID *)&TimerCtrlReg);\r
+ ArmWriteCntvCtl (TimerCtrlReg);\r
}\r
\r
VOID\r
{\r
UINTN TimerCtrlReg;\r
\r
- ArmArchTimerReadReg (CntvCtl, (VOID *)&TimerCtrlReg);\r
+ TimerCtrlReg = ArmReadCntvCtl ();\r
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r
- ArmArchTimerWriteReg (CntvCtl, (VOID *)&TimerCtrlReg);\r
+ ArmWriteCntvCtl (TimerCtrlReg);\r
}\r
\r
VOID\r
IN UINTN FreqInHz\r
)\r
{\r
- ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);\r
+ ArmWriteCntFrq (FreqInHz);\r
}\r
\r
UINTN\r
VOID\r
)\r
{\r
- UINTN ArchTimerFreq = 0;\r
- ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);\r
- return ArchTimerFreq;\r
+ return ArmReadCntFrq ();\r
}\r
\r
UINTN\r
VOID\r
)\r
{\r
- UINTN ArchTimerValue;\r
- ArmArchTimerReadReg (CntvTval, (VOID *)&ArchTimerValue);\r
-\r
- return ArchTimerValue;\r
+ return ArmReadCntvTval ();\r
}\r
\r
\r
IN UINTN Value\r
)\r
{\r
- ArmArchTimerWriteReg (CntvTval, (VOID *)&Value);\r
+ ArmWriteCntvTval (Value);\r
}\r
\r
UINT64\r
VOID\r
)\r
{\r
- UINT64 SystemCount;\r
- ArmArchTimerReadReg (CntvCt, (VOID *)&SystemCount);\r
-\r
- return SystemCount;\r
+ return ArmReadCntvCt ();\r
}\r
\r
UINTN\r
VOID\r
)\r
{\r
- UINTN Value;\r
- ArmArchTimerReadReg (CntvCtl, (VOID *)&Value);\r
-\r
- return Value;\r
+ return ArmReadCntvCtl ();\r
}\r
\r
VOID\r
UINTN Value\r
)\r
{\r
- ArmArchTimerWriteReg (CntvCtl, (VOID *)&Value);\r
+ ArmWriteCntvCtl (Value);\r
}\r
\r
UINT64\r
VOID\r
)\r
{\r
- UINT64 Value;\r
- ArmArchTimerReadReg (CntvCval, (VOID *)&Value);\r
-\r
- return Value;\r
+ return ArmReadCntvCval ();\r
}\r
\r
VOID\r
IN UINT64 Value\r
)\r
{\r
- ArmArchTimerWriteReg (CntvCval, (VOID *)&Value);\r
+ ArmWriteCntvCval (Value);\r
}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Chipset/AArch64.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include "AArch64Lib.h"\r
-#include "ArmLibPrivate.h"\r
-#include <Library/ArmArchTimer.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerReadReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- OUT VOID *DstBuf\r
- )\r
-{\r
- // Check if the Generic/Architecture timer is implemented\r
- if (ArmIsArchTimerImplemented ()) {\r
-\r
- switch (Reg) {\r
-\r
- case CntFrq:\r
- *((UINTN *)DstBuf) = ArmReadCntFrq ();\r
- break;\r
-\r
- case CntPct:\r
- *((UINT64 *)DstBuf) = ArmReadCntPct ();\r
- break;\r
-\r
- case CntkCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntkCtl();\r
- break;\r
-\r
- case CntpTval:\r
- *((UINTN *)DstBuf) = ArmReadCntpTval ();\r
- break;\r
-\r
- case CntpCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r
- break;\r
-\r
- case CntvTval:\r
- *((UINTN *)DstBuf) = ArmReadCntvTval ();\r
- break;\r
-\r
- case CntvCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r
- break;\r
-\r
- case CntvCt:\r
- *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r
- break;\r
-\r
- case CntpCval:\r
- *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r
- break;\r
-\r
- case CntvCval:\r
- *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r
- break;\r
-\r
- case CntvOff:\r
- *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r
- break;\r
-\r
- case CnthCtl:\r
- case CnthpTval:\r
- case CnthpCtl:\r
- case CnthpCval:\r
- DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
- }\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
- ASSERT (0);\r
- }\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerWriteReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- IN VOID *SrcBuf\r
- )\r
-{\r
- // Check if the Generic/Architecture timer is implemented\r
- if (ArmIsArchTimerImplemented ()) {\r
-\r
- switch (Reg) {\r
-\r
- case CntFrq:\r
- ArmWriteCntFrq (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntPct:\r
- DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r
- break;\r
-\r
- case CntkCtl:\r
- ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntpTval:\r
- ArmWriteCntpTval (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntpCtl:\r
- ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvTval:\r
- ArmWriteCntvTval (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvCtl:\r
- ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvCt:\r
- DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r
- break;\r
-\r
- case CntpCval:\r
- ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r
- break;\r
-\r
- case CntvCval:\r
- ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r
- break;\r
-\r
- case CntvOff:\r
- ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r
- break;\r
-\r
- case CnthCtl:\r
- case CnthpTval:\r
- case CnthpCtl:\r
- case CnthpCval:\r
- DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
- }\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
- ASSERT (0);\r
- }\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Chipset/ArmV7.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include "ArmV7Lib.h"\r
-#include "ArmLibPrivate.h"\r
-#include <Library/ArmArchTimer.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerReadReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- OUT VOID *DstBuf\r
- )\r
-{\r
- // Check if the Generic/Architecture timer is implemented\r
- if (ArmIsArchTimerImplemented ()) {\r
- switch (Reg) {\r
- case CntFrq:\r
- *((UINTN *)DstBuf) = ArmReadCntFrq ();\r
- return;\r
-\r
- case CntPct:\r
- *((UINT64 *)DstBuf) = ArmReadCntPct ();\r
- return;\r
-\r
- case CntkCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntkCtl();\r
- return;\r
-\r
- case CntpTval:\r
- *((UINTN *)DstBuf) = ArmReadCntpTval ();\r
- return;\r
-\r
- case CntpCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r
- return;\r
-\r
- case CntvTval:\r
- *((UINTN *)DstBuf) = ArmReadCntvTval ();\r
- return;\r
-\r
- case CntvCtl:\r
- *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r
- return;\r
-\r
- case CntvCt:\r
- *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r
- return;\r
-\r
- case CntpCval:\r
- *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r
- return;\r
-\r
- case CntvCval:\r
- *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r
- return;\r
-\r
- case CntvOff:\r
- *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r
- return;\r
-\r
- case CnthCtl:\r
- case CnthpTval:\r
- case CnthpCtl:\r
- case CnthpCval:\r
- DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
- }\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
- ASSERT (0);\r
- }\r
-\r
- *((UINT64 *)DstBuf) = 0;\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmArchTimerWriteReg (\r
- IN ARM_ARCH_TIMER_REGS Reg,\r
- IN VOID *SrcBuf\r
- )\r
-{\r
- // Check if the Generic/Architecture timer is implemented\r
- if (ArmIsArchTimerImplemented ()) {\r
-\r
- switch (Reg) {\r
-\r
- case CntFrq:\r
- ArmWriteCntFrq (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntPct:\r
- DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r
- break;\r
-\r
- case CntkCtl:\r
- ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntpTval:\r
- ArmWriteCntpTval (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntpCtl:\r
- ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvTval:\r
- ArmWriteCntvTval (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvCtl:\r
- ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r
- break;\r
-\r
- case CntvCt:\r
- DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r
- break;\r
-\r
- case CntpCval:\r
- ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r
- break;\r
-\r
- case CntvCval:\r
- ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r
- break;\r
-\r
- case CntvOff:\r
- ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r
- break;\r
-\r
- case CnthCtl:\r
- case CnthpTval:\r
- case CnthpCtl:\r
- case CnthpCval:\r
- DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
- }\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
- ASSERT (0);\r
- }\r
-}\r
\r
[Sources.ARM]\r
Arm/ArmV7Lib.c\r
- Arm/ArmV7ArchTimer.c\r
\r
Arm/ArmLibSupport.S | GCC\r
Arm/ArmLibSupportV7.S | GCC\r
\r
[Sources.AARCH64]\r
AArch64/AArch64Lib.c\r
- AArch64/AArch64ArchTimer.c\r
\r
AArch64/ArmLibSupport.S\r
AArch64/ArmLibSupportV8.S\r