OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35

The comments in the code should speak for themselves; here we note only
two facts:

- The PCI config space writes (to the PCIEXBAR register) are performed
  using the 0xCF8 / 0xCFC IO ports, by virtue of PciLib being resolved to
  BasePciLibCf8. (This library resolution will permanently remain in place
  for the PEI phase.)

- Since PCIEXBAR counts as a chipset register, it is the responsibility of
  the firmware to reprogram it at S3 resume. Therefore
  PciExBarInitialization() is called regardless of the boot path. (Marcel
  recently posted patches for SeaBIOS that implement this.)

This patch suffices to enable PCIEXBAR (and the dependent ACPI table
generation in QEMU), for the sake of "PCIeHotplug" in the Linux guest:

  ACPI: MCFG 0x000000007E17F000 00003C
        (v01 BOCHS  BXPCMCFG 00000001 BXPC 00000001)
  PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0x80000000-0x8fffffff]
       (base 0x80000000)
  PCI: MMCONFIG at [mem 0x80000000-0x8fffffff] reserved in E820
  acpi PNP0A08:00: _OSC: OS supports
                   [ExtendedConfig ASPM ClockPM Segments MSI]
  acpi PNP0A08:00: _OSC: OS now controls
                   [PCIeHotplug PME AER PCIeCapability]

In the following patches, we'll equip the core PCI host bridge / root
bridge driver and the rest of DXE as well to utilize ECAM on Q35.

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michał Zegan <webczat_200@poczta.onet.pl>
Ref: https://github.com/tianocore/edk2/issues/32
Ref: http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/10548
Suggested-by: Marcel Apfelbaum <marcel@redhat.com>
Reported-by: Michał Zegan <webczat_200@poczta.onet.pl>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 9b603f001fe5b25394e07481bb83d48eb4f7dedf..aae1972950ee5f2cd1e1f43ab3b3d6b3c6679932 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -395,6 +395,14 @@
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
 !endif\r
 \r
+  # This PCD is used to set the base address of the PCI express hierarchy. It\r
+  # is only consulted when OVMF runs on Q35. In that case it is programmed into\r
+  # the PCIEXBAR register.\r
+  #\r
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
+  # never lets the RAM below 4 GB exceed 2 GB.\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
+\r
 !ifdef $(SOURCE_DEBUG_ENABLE)\r
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
 !endif\r

diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1d68eb95d69e79f441caf10848f55ed15258286c..0422dda09fbe584c95c7c00a136be72d81f20bd9 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -400,6 +400,14 @@
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
 !endif\r
 \r
+  # This PCD is used to set the base address of the PCI express hierarchy. It\r
+  # is only consulted when OVMF runs on Q35. In that case it is programmed into\r
+  # the PCIEXBAR register.\r
+  #\r
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
+  # never lets the RAM below 4 GB exceed 2 GB.\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
+\r
 !ifdef $(SOURCE_DEBUG_ENABLE)\r
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
 !endif\r

diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index b971ee8bb56b2f6c61a44844bd7490c1d156b734..18517e337649474be89ff98665e3c54f8efa83e5 100644 (file)
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -400,6 +400,14 @@
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
 !endif\r
 \r
+  # This PCD is used to set the base address of the PCI express hierarchy. It\r
+  # is only consulted when OVMF runs on Q35. In that case it is programmed into\r
+  # the PCIEXBAR register.\r
+  #\r
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
+  # never lets the RAM below 4 GB exceed 2 GB.\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
+\r
 !ifdef $(SOURCE_DEBUG_ENABLE)\r
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
 !endif\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 8e4da41001e1248d0e255c88ee3e653a4214b19c..0fc227803a84366e5f339402173ad0c04b7b0a77 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -212,17 +212,20 @@ MemMapInitialization (
 \r
   if (!mXen) {\r
     UINT32  TopOfLowRam;\r
+    UINT64  PciExBarBase;\r
     UINT32  PciBase;\r
     UINT32  PciSize;\r
 \r
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
-      // On Q35 machine types that QEMU intends to support in the long term,\r
-      // QEMU never lets the RAM below 4 GB exceed 2 GB.\r
+      // The MMCONFIG area is expected to fall between the top of low RAM and\r
+      // the base of the 32-bit PCI host aperture.\r
       //\r
-      PciBase = BASE_2GB;\r
-      ASSERT (TopOfLowRam <= PciBase);\r
+      PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+      ASSERT (TopOfLowRam <= PciExBarBase);\r
+      ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
+      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
     } else {\r
       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
     }\r
@@ -248,6 +251,30 @@ MemMapInitialization (
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+      //\r
+      // Note: there should be an\r
+      //\r
+      //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
+      //\r
+      // call below, just like the one above for RCBA. However, Linux insists\r
+      // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
+      // "reserved memory" -- Linux does not content itself with a simple gap\r
+      // in the memory map wherever the MCFG ACPI table points to.\r
+      //\r
+      // This appears to be a safety measure. The PCI Firmware Specification\r
+      // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
+      // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
+      // [...]". (Emphasis added here.)\r
+      //\r
+      // Normally we add memory resource descriptor HOBs in\r
+      // QemuInitializeRam(), and pre-allocate from those with memory\r
+      // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
+      // is most definitely not RAM; so, as an exception, cover it with\r
+      // uncacheable reserved memory right here.\r
+      //\r
+      AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
+      BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r
+        EfiReservedMemoryType);\r
     }\r
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
   }\r
@@ -316,6 +343,47 @@ NoexecDxeInitialization (
   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
 }\r
 \r
+VOID\r
+PciExBarInitialization (\r
+  VOID\r
+  )\r
+{\r
+  union {\r
+    UINT64 Uint64;\r
+    UINT32 Uint32[2];\r
+  } PciExBarBase;\r
+\r
+  //\r
+  // We only support the 256MB size for the MMCONFIG area:\r
+  // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
+  //\r
+  // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
+  // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
+  //\r
+  // Note that (b) also ensures that the minimum address width we have\r
+  // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
+  // for DXE's page tables to cover the MMCONFIG area.\r
+  //\r
+  PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+  ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
+  ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
+\r
+  //\r
+  // Clear the PCIEXBAREN bit first, before programming the high register.\r
+  //\r
+  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
+\r
+  //\r
+  // Program the high register. Then program the low register, setting the\r
+  // MMCONFIG area size and enabling decoding at once.\r
+  //\r
+  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
+  PciWrite32 (\r
+    DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
+    PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
+    );\r
+}\r
+\r
 VOID\r
 MiscInitialization (\r
   VOID\r
@@ -393,6 +461,11 @@ MiscInitialization (
       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
       );\r
+\r
+    //\r
+    // Set PCI Express Register Range Base Address\r
+    //\r
+    PciExBarInitialization ();\r
   }\r
 }\r
 \r

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf
index 8480839efc8ec2d6016f019094b18c518551d601..6dc5ff079f53f489a60ed724e17664154cca3721 100644 (file)
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -94,6 +94,9 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\r
 \r
+[FixedPcd]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
 [FeaturePcd]\r
   gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire\r
 \r