ArmPkg/GenericWatchdogDxe: Declare MMIO PCDs as UINT64

PcdGenericWatchdogControlBase & PcdGenericWatchdogRefreshBase
are declared as UINT32 values in ArmPkg.dec, but for platforms
with addresses in the memory range above 4GB this causes build
error F000: Too large PCD value for datum type [UINT32]
of PCD gArmTokenSpaceGuid.PcdGenericWatchdogControlBase

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=361
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 090ed99513669e32aee2f083e1dcf8327be40842..8e9cf199becc65a9f6fe08e2d5b216bc2af4c31d 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -2,7 +2,7 @@
 # ARM processor package.\r
 #\r
 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
 #\r
 #    This program and the accompanying materials\r
 #    are licensed and made available under the terms and conditions of the BSD License\r
@@ -252,8 +252,8 @@
   # ARM Generic Watchdog\r
   #\r
 \r
-  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007\r
-  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008\r
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
 \r
   #\r

diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
index 578fd1e85f8e11b42e546f92123fd041a2d3b153..9e2aebcfd5e557269bbc36556dbcbc8f6809aeb0 100644 (file)
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2013-2017, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD\r
@@ -15,12 +15,12 @@
 #define __GENERIC_WATCHDOG_H__\r
 \r
 // Refresh Frame:\r
-#define GENERIC_WDOG_REFRESH_REG              ((UINT32)FixedPcdGet32 (PcdGenericWatchdogRefreshBase) + 0x000)\r
+#define GENERIC_WDOG_REFRESH_REG              ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)\r
 \r
 // Control Frame:\r
-#define GENERIC_WDOG_CONTROL_STATUS_REG       ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x000)\r
-#define GENERIC_WDOG_OFFSET_REG               ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x008)\r
-#define GENERIC_WDOG_COMPARE_VALUE_REG        ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x010)\r
+#define GENERIC_WDOG_CONTROL_STATUS_REG       ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)\r
+#define GENERIC_WDOG_OFFSET_REG               ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)\r
+#define GENERIC_WDOG_COMPARE_VALUE_REG        ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)\r
 \r
 // Values of bit 0 of the Control/Status Register\r
 #define GENERIC_WDOG_ENABLED          1\r