OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script

EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to
access in UEFI encoding, not in edk2/PciLib encoding.

Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with
it, store the ICH9_GEN_PMCON_1 register's address to the boot script in
UEFI representation.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 4dc2c39901c13523660e4adf3a446ef82f646b66..f480455ae4326ba583ff29052ba79e275651a75f 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -19,6 +19,9 @@
 #define __Q35_MCH_ICH9_H__\r
 \r
 #include <Library/PciLib.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiSpec.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
 \r
 //\r
 // Host Bridge Device ID (DID) value for Q35/MCH\r
@@ -75,6 +78,9 @@
 #define POWER_MGMT_REGISTER_Q35(Offset) \\r
   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))\r
 \r
+#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \\r
+  EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))\r
+\r
 #define ICH9_PMBASE               0x40\r
 #define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
                                      BIT10 | BIT9  | BIT8  | BIT7)\r

diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c
index 82549b0a7e353153f2678b50ae5901dfd066303c..6c03e17a3a8d8a8415ace7b2744304c956abc038 100644 (file)
--- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c
+++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c
@@ -311,6 +311,7 @@ OnS3SaveStateInstalled (
   EFI_STATUS                 Status;\r
   EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;\r
   UINT32                     SmiEnOrMask, SmiEnAndMask;\r
+  UINT64                     GenPmCon1Address;\r
   UINT16                     GenPmCon1OrMask, GenPmCon1AndMask;\r
 \r
   ASSERT (Event == mS3SaveStateInstalled);\r
@@ -342,13 +343,15 @@ OnS3SaveStateInstalled (
     CpuDeadLoop ();\r
   }\r
 \r
+  GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS (\r
+                       ICH9_GEN_PMCON_1);\r
   GenPmCon1OrMask  = ICH9_GEN_PMCON_1_SMI_LOCK;\r
   GenPmCon1AndMask = MAX_UINT16;\r
   Status = S3SaveState->Write (\r
                           S3SaveState,\r
                           EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,\r
                           EfiBootScriptWidthUint16,\r
-                          (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
+                          GenPmCon1Address,\r
                           &GenPmCon1OrMask,\r
                           &GenPmCon1AndMask\r
                           );\r