Some SdMmc host controllers are run by clocks with different
frequency than it is reflected in Capabilities Register 1.
It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq
field value of the Capability Register 1 is zero, the clock
frequency must be obtained via another method.
Because the bitfield is only 8 bits wide, a maximum value
that could be obtained from hardware is 255MHz.
In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq
member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient
to be used for setting the clock speed in SdMmcHcClockSupply
function.
This patch adds new UINT32 array ('BaseClkFreq[]') to
SD_MMC_HC_PRIVATE_DATA structure for specifying
the input clock speed for each slot of the host controller.
All routines that are used for clock configuration are
updated accordingly.
This patch also adds new IN OUT BaseClockFreq field
in the Capability callback of the SdMmcOverride,
protocol which allows to update BaseClkFreq value.
The patch reuses original commit from edk2-platforms:
20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock
frequency")
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
//\r
// Convert the clock freq unit from MHz to KHz.\r
//\r
- Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->Capability[Slot]);\r
+ Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot]);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
return Status;\r
}\r
\r
- ASSERT (Private->Capability[Slot].BaseClkFreq != 0);\r
+ ASSERT (Private->BaseClkFreq[Slot] != 0);\r
//\r
// Check if the Host Controller support 8bits bus width.\r
//\r
return Status;\r
}\r
\r
- Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);\r
+ Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot]);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
goto Error;\r
}\r
\r
- SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);\r
+ SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);\r
\r
gBS->Stall (1000);\r
\r
if (EFI_ERROR (Status)) {\r
continue;\r
}\r
+\r
+ Private->BaseClkFreq[Slot] = Private->Capability[Slot].BaseClkFreq;\r
+\r
if (mOverride != NULL && mOverride->Capability != NULL) {\r
Status = mOverride->Capability (\r
Controller,\r
Slot,\r
- &Private->Capability[Slot]);\r
+ &Private->Capability[Slot],\r
+ &Private->BaseClkFreq[Slot]\r
+ );\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",\r
__FUNCTION__, Status));\r
}\r
}\r
DumpCapabilityReg (Slot, &Private->Capability[Slot]);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Slot[%d] Base Clock Frequency: %dMHz\n",\r
+ Slot,\r
+ Private->BaseClkFreq[Slot]\r
+ ));\r
\r
Support64BitDma &= Private->Capability[Slot].SysBus64;\r
\r
UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];\r
\r
UINT32 ControllerVersion;\r
+\r
+ //\r
+ // Some controllers may require to override base clock frequency\r
+ // value stored in Capabilities Register 1.\r
+ //\r
+ UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];\r
} SD_MMC_HC_PRIVATE_DATA;\r
\r
#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
- @param[in] Capability The capability of the slot.\r
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
IN UINT64 ClockFreq,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN UINT32 BaseClkFreq\r
)\r
{\r
EFI_STATUS Status;\r
- UINT32 BaseClkFreq;\r
UINT32 SettingFreq;\r
UINT32 Divisor;\r
UINT32 Remainder;\r
//\r
// Calculate a divisor for SD clock frequency\r
//\r
- ASSERT (Capability.BaseClkFreq != 0);\r
+ ASSERT (BaseClkFreq != 0);\r
\r
- BaseClkFreq = Capability.BaseClkFreq;\r
if (ClockFreq == 0) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Capability The capability of the slot.\r
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
SdMmcHcInitClockFreq (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN UINT32 BaseClkFreq\r
)\r
{\r
EFI_STATUS Status;\r
UINT32 InitFreq;\r
\r
//\r
- // Calculate a divisor for SD clock frequency\r
+ // According to SDHCI specification ver. 4.2, BaseClkFreq field value of\r
+ // the Capability Register 1 can be zero, which means a need for obtaining\r
+ // the clock frequency via another method. Fail in case it is not updated\r
+ // by SW at this point.\r
//\r
- if (Capability.BaseClkFreq == 0) {\r
+ if (BaseClkFreq == 0) {\r
//\r
// Don't support get Base Clock Frequency information via another method\r
//\r
// Supply 400KHz clock frequency at initialization phase.\r
//\r
InitFreq = 400;\r
- Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);\r
+ Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);\r
return Status;\r
}\r
\r
PciIo = Private->PciIo;\r
Capability = Private->Capability[Slot];\r
\r
- Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);\r
+ Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
- @param[in] Capability The capability of the slot.\r
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
IN UINT64 ClockFreq,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN UINT32 BaseClkFreq\r
);\r
\r
/**\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Capability The capability of the slot.\r
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
SdMmcHcInitClockFreq (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
- IN SD_MMC_HC_SLOT_CAP Capability\r
+ IN UINT32 BaseClkFreq\r
);\r
\r
/**\r
#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \\r
{ 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } }\r
\r
-#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x1\r
+#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x2\r
\r
typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE;\r
\r
@param[in] ControllerHandle The EFI_HANDLE of the controller.\r
@param[in] Slot The 0 based slot index.\r
@param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.\r
+ @param[in,out] BaseClkFreq The base clock frequency value that\r
+ optionally can be updated.\r
\r
@retval EFI_SUCCESS The override function completed successfully.\r
@retval EFI_NOT_FOUND The specified controller or slot does not exist.\r
(EFIAPI * EDKII_SD_MMC_CAPABILITY) (\r
IN EFI_HANDLE ControllerHandle,\r
IN UINT8 Slot,\r
- IN OUT VOID *SdMmcHcSlotCapability\r
+ IN OUT VOID *SdMmcHcSlotCapability,\r
+ IN OUT UINT32 *BaseClkFreq\r
);\r
\r
/**\r
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