--- /dev/null
+/** @file\r
+ DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)\r
+ Virtualization Technology for Directed I/O (VT-D) Architecture Specification.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture\r
+ Specification v2.4, Dated June 2016.\r
+ http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf\r
+\r
+ @par Glossary:\r
+ - HPET - High Precision Event Timer\r
+ - NUMA - Non-uniform Memory Access\r
+**/\r
+#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_\r
+#define _DMA_REMAPPING_REPORTING_TABLE_H_\r
+\r
+#pragma pack(1)\r
+\r
+///\r
+/// DMA-Remapping Reporting Structure definitions from section 8.1\r
+///@{\r
+#define EFI_ACPI_DMAR_REVISION 0x01\r
+\r
+#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0\r
+#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1\r
+///@}\r
+\r
+///\r
+/// Remapping Structure Types definitions from section 8.2\r
+///@{\r
+#define EFI_ACPI_DMAR_TYPE_DRHD 0x00\r
+#define EFI_ACPI_DMAR_TYPE_RMRR 0x01\r
+#define EFI_ACPI_DMAR_TYPE_ATSR 0x02\r
+#define EFI_ACPI_DMAR_TYPE_RHSA 0x03\r
+#define EFI_ACPI_DMAR_TYPE_ANDD 0x04\r
+///@}\r
+\r
+///\r
+/// DMA-Remapping Hardware Unit definitions from section 8.3\r
+///\r
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0\r
+\r
+///\r
+/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1\r
+///@{\r
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01\r
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02\r
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03\r
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04\r
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05\r
+///@}\r
+\r
+///\r
+/// Root Port ATS Capability Reporting Structure definitions from section 8.5\r
+///\r
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0\r
+\r
+///\r
+/// Definition for DMA Remapping Structure Header\r
+///\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+} EFI_ACPI_DMAR_STRUCTURE_HEADER;\r
+\r
+///\r
+/// Definition for DMA-Remapping PCI Path\r
+///\r
+typedef struct {\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+} EFI_ACPI_DMAR_PCI_PATH;\r
+\r
+///\r
+/// Device Scope Structure is defined in section 8.3.1\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved2;\r
+ UINT8 EnumerationId;\r
+ UINT8 StartBusNumber;\r
+} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;\r
+\r
+/**\r
+ DMA-remapping hardware unit definition (DRHD) structure is defined in\r
+ section 8.3. This uniquely represents a remapping hardware unit present\r
+ in the platform. There must be at least one instance of this structure\r
+ for each PCI segment in the platform.\r
+**/\r
+typedef struct {\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ /**\r
+ - Bit[0]: INCLUDE_PCI_ALL\r
+ - If Set, this remapping hardware unit has under its scope all\r
+ PCI compatible devices in the specified Segment, except devices\r
+ reported under the scope of other remapping hardware units for\r
+ the same Segment.\r
+ - If Clear, this remapping hardware unit has under its scope only\r
+ devices in the specified Segment that are explicitly identified\r
+ through the DeviceScope field.\r
+ - Bits[7:1] Reserved.\r
+ **/\r
+ UINT8 Flags;\r
+ UINT8 Reserved;\r
+ ///\r
+ /// The PCI Segment associated with this unit.\r
+ ///\r
+ UINT16 SegmentNumber;\r
+ ///\r
+ /// Base address of remapping hardware register-set for this unit.\r
+ ///\r
+ UINT64 RegisterBaseAddress;\r
+} EFI_ACPI_DMAR_DRHD_HEADER;\r
+\r
+/**\r
+ Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4\r
+ Reserved memory ranges that may be DMA targets may be reported through the\r
+ RMRR structures, along with the devices that requires access to the specified\r
+ reserved memory region.\r
+**/\r
+typedef struct {\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ UINT8 Reserved[2];\r
+ ///\r
+ /// PCI Segment Number associated with devices identified through\r
+ /// the Device Scope field.\r
+ ///\r
+ UINT16 SegmentNumber;\r
+ ///\r
+ /// Base address of 4KB-aligned reserved memory region\r
+ ///\r
+ UINT64 ReservedMemoryRegionBaseAddress;\r
+ /**\r
+ Last address of the reserved memory region. Value in this field must be\r
+ greater than the value in Reserved Memory Region Base Address field.\r
+ The reserved memory region size (Limit - Base + 1) must be an integer\r
+ multiple of 4KB.\r
+ **/\r
+ UINT64 ReservedMemoryRegionLimitAddress;\r
+} EFI_ACPI_DMAR_RMRR_HEADER;\r
+\r
+/**\r
+ Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.\r
+ This structure is applicable only for platforms supporting Device-TLBs as\r
+ reported through the Extended Capability Register. For each PCI Segment in\r
+ the platform that supports Device-TLBs, BIOS provides an ATSR structure. The\r
+ ATSR structures identifies PCI-Express Root-Ports supporting Address\r
+ Translation Services (ATS) transactions. Software must enable ATS on endpoint\r
+ devices behind a Root Port only if the Root Port is reported as supporting\r
+ ATS transactions.\r
+**/\r
+typedef struct {\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ /**\r
+ - Bit[0]: ALL_PORTS:\r
+ - If Set, indicates all PCI Express Root Ports in the specified\r
+ PCI Segment supports ATS transactions.\r
+ - If Clear, indicates ATS transactions are supported only on\r
+ Root Ports identified through the Device Scope field.\r
+ - Bits[7:1] Reserved.\r
+ **/\r
+ UINT8 Flags;\r
+ UINT8 Reserved;\r
+ ///\r
+ /// The PCI Segment associated with this ATSR structure\r
+ ///\r
+ UINT16 SegmentNumber;\r
+} EFI_ACPI_DMAR_ATSR_HEADER;\r
+\r
+/**\r
+ Remapping Hardware Static Affinity (RHSA) is an optional structure defined\r
+ in section 8.6. This is intended to be used only on NUMA platforms with\r
+ Remapping hardware units and memory spanned across multiple nodes.\r
+ When used, there must be a RHSA structure for each Remapping hardware unit\r
+ reported through DRHD structure.\r
+**/\r
+typedef struct {\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ UINT8 Reserved[4];\r
+ ///\r
+ /// Register Base Address of this Remap hardware unit reported in the\r
+ /// corresponding DRHD structure.\r
+ ///\r
+ UINT64 RegisterBaseAddress;\r
+ ///\r
+ /// Proximity Domain to which the Remap hardware unit identified by the\r
+ /// Register Base Address field belongs.\r
+ ///\r
+ UINT32 ProximityDomain;\r
+} EFI_ACPI_DMAR_RHSA_HEADER;\r
+\r
+/**\r
+ An ACPI Name-space Device Declaration (ANDD) structure is defined in section\r
+ 8.7 and uniquely represents an ACPI name-space enumerated device capable of\r
+ issuing DMA requests in the platform. ANDD structures are used in conjunction\r
+ with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.\r
+**/\r
+typedef struct {\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ UINT8 Reserved[3];\r
+ /**\r
+ Each ACPI device enumerated through an ANDD structure must have a unique\r
+ value for this field. To report an ACPI device with ACPI Device Number\r
+ value of X, under the scope of a DRHD unit, a Device-Scope entry of type\r
+ ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.\r
+ The Start Bus Number and Path fields in the Device-Scope together\r
+ provides the 16-bit source-id allocated by platform for the ACPI device.\r
+ **/\r
+ UINT8 AcpiDeviceNumber;\r
+} EFI_ACPI_DMAR_ANDD_HEADER;\r
+\r
+/**\r
+ DMA Remapping Reporting Structure Header as defined in section 8.1\r
+ This header will be followed by list of Remapping Structures listed below\r
+ - DMA Remapping Hardware Unit Definition (DRHD)\r
+ - Reserved Memory Region Reporting (RMRR)\r
+ - Root Port ATS Capability Reporting (ATSR)\r
+ - Remapping Hardware Static Affinity (RHSA)\r
+ - ACPI Name-space Device Declaration (ANDD)\r
+ These structure types must by reported in numerical order.\r
+ i.e., All remapping structures of type 0 (DRHD) enumerated before remapping\r
+ structures of type 1 (RMRR), and so forth.\r
+**/\r
+typedef struct {\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ /**\r
+ This field indicates the maximum DMA physical addressability supported by\r
+ this platform. The system address map reported by the BIOS indicates what\r
+ portions of this addresses are populated. The Host Address Width (HAW) of\r
+ the platform is computed as (N+1), where N is the value reported in this\r
+ field.\r
+ For example, for a platform supporting 40 bits of physical addressability,\r
+ the value of 100111b is reported in this field.\r
+ **/\r
+ UINT8 HostAddressWidth;\r
+ /**\r
+ - Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt\r
+ remapping. If Set, the platform supports interrupt remapping.\r
+ - Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform\r
+ firmware may Set this field to request system software to opt\r
+ out of enabling Extended xAPIC (X2APIC) mode. This field is\r
+ valid only when the INTR_REMAP field (bit 0) is Set.\r
+ - Bits[7:2] Reserved.\r
+ **/\r
+ UINT8 Flags;\r
+ UINT8 Reserved[10];\r
+} EFI_ACPI_DMAR_HEADER;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
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