/** @file\r
\r
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
-Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>\r
+Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials are licensed and made available\r
under the terms and conditions of the BSD License which accompanies this\r
\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
\r
+ case R_AARCH64_ADR_PREL_LO21:\r
+ if (Rel->r_addend != 0 ) { /* TODO */\r
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_ADR_PREL_LO21 Need to fixup with addend!.");\r
+ }\r
+ break;\r
+\r
+ case R_AARCH64_CONDBR19:\r
+ if (Rel->r_addend != 0 ) { /* TODO */\r
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CONDBR19 Need to fixup with addend!.");\r
+ }\r
+ break;\r
+\r
case R_AARCH64_LD_PREL_LO19:\r
if (Rel->r_addend != 0 ) { /* TODO */\r
Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");\r
} else if (mEhdr->e_machine == EM_AARCH64) {\r
// AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
+ case R_AARCH64_ADR_PREL_LO21:\r
+ break;\r
+\r
+ case R_AARCH64_CONDBR19:\r
+ break;\r
+\r
case R_AARCH64_LD_PREL_LO19:\r
break;\r
\r