--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Chipset/ArmV7.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r
+GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r
+// Dirty hack to get the Fixed value of GicDistributorBase\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)\r
+\r
+\r
+// VOID\r
+// ArmCpuSynchronizeWait (\r
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+// );\r
+ASM_PFX(ArmCpuSynchronizeWait):\r
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
+ beq ArmWaitGicDistributorEnabled\r
+ b CArmCpuSynchronizeWait\r
+\r
+// IN None\r
+ArmWaitGicDistributorEnabled:\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)\r
+ ldr r0, [r0]\r
+_WaitGicDistributor:\r
+ ldr r1, [r0, #ARM_GIC_ICDDCR]\r
+ cmp r1, #1\r
+ bne _WaitGicDistributor\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Chipset/ArmV7.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmCpuSynchronizeWait\r
+ IMPORT CArmCpuSynchronizeWait\r
+ // Dirty hack to get the Fixed value of GicDistributorBase\r
+ IMPORT _gPcd_FixedAtBuild_PcdGicDistributorBase\r
+\r
+ PRESERVE8\r
+ AREA ArmCortexA15Helper, CODE, READONLY\r
+\r
+// VOID\r
+// ArmCpuSynchronizeWait (\r
+// IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+// );\r
+ArmCpuSynchronizeWait\r
+ cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r
+ beq ArmWaitGicDistributorEnabled\r
+ b CArmCpuSynchronizeWait\r
+\r
+// IN None\r
+ArmWaitGicDistributorEnabled\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)\r
+ ldr r0, [r0]\r
+_WaitGicDistributor\r
+ ldr r1, [r0, #ARM_GIC_ICDDCR]\r
+ cmp r1, #1\r
+ bne _WaitGicDistributor\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2011, ARM Limited. All rights reserved.\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/ArmV7ArchTimerLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+VOID\r
+ArmCpuSynchronizeSignal (\r
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+ )\r
+{\r
+ if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r
+ // Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor\r
+ // to be enabled (done by the Sec module itself) as a way to know when the Init Boot\r
+ // Mem as been initialized\r
+ } else {\r
+ // Send SGI to all Secondary core to wake them up from WFI state.\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ }\r
+}\r
+\r
+VOID\r
+CArmCpuSynchronizeWait (\r
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event\r
+ )\r
+{\r
+ // Waiting for the SGI from the primary core\r
+ ArmCallWFI ();\r
+\r
+ // Acknowledge the interrupt and send End of Interrupt signal.\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
+}\r
+\r
+VOID\r
+ArmCpuSetup (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ // Check if Architectural Timer frequency is valid number (should not be 0)\r
+ ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));\r
+ ASSERT(ArmIsArchTimerImplemented () != 0);\r
+\r
+ // Enable SWP instructions\r
+ ArmEnableSWPInstruction ();\r
+\r
+ // Enable program flow prediction, if supported.\r
+ ArmEnableBranchPrediction ();\r
+\r
+ // Note: System Counter frequency can only be set in Secure privileged mode,\r
+ // if security extensions are implemented.\r
+ ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r
+\r
+ /*// If MPCore then Enable the SCU\r
+ if (ArmIsMpCore()) {\r
+ ArmEnableScu ();\r
+ }*/\r
+}\r
+\r
+\r
+VOID\r
+ArmCpuSetupSmpNonSecure (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ //ArmSetAuxCrBit (A15_FEATURE_SMP);\r
+\r
+ /*// Make the SCU accessible in Non Secure world\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
+ ScuBase = ArmGetScuBaseAddress();\r
+\r
+ // Allow NS access to SCU register\r
+ MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
+ // Allow NS access to Private Peripherals\r
+ MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
+ }*/\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmCortexA15Lib\r
+ FILE_GUID = 501b1c8f-21d5-4ef5-a565-435b7f0aae2d\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmCpuLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+\r
+[LibraryClasses]\r
+ ArmLib\r
+ ArmGicSecLib\r
+ IoLib\r
+ PcdLib\r
+\r
+[Sources.common]\r
+ ArmCortexA15Lib.c\r
+ ArmCortexA15Helper.asm | RVCT\r
+ ArmCortexA15Helper.S | GCC\r
+\r
+[FeaturePcd]\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\r
--- /dev/null
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmVExpressPkg-RTSM-A15\r
+ PLATFORM_GUID = 1665b5b1-529d-4ba1-bd51-c3c9b29a2274\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15\r
+ SUPPORTED_ARCHITECTURES = ARM\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.fdf\r
+\r
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
+\r
+[LibraryClasses.common]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
+ \r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
+ LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf\r
+\r
+ #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
+\r
+ # ARM PL390 General Interrupt Driver in Secure and Non-secure\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+\r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf \r
+\r
+[LibraryClasses.common.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressSecLib.inf\r
+[BuildOptions]\r
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+ \r
+ XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+!ifdef $(EDK2_SKIP_PEICORE)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE\r
+!endif\r
+ \r
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
+ # It could be set FALSE to save size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ \r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"\r
+ \r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-RTSM"\r
+\r
+ #\r
+ # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
+\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+ \r
+ # Stacks for MPCores in Secure World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000\r
+ \r
+ # Stacks for MPCores in Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100\r
+ \r
+ # Stacks for MPCores in Normal World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+ \r
+ # System Memory (1GB) \r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000\r
+ \r
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
+ \r
+ #\r
+ # ARM Pcds\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
+ \r
+ #\r
+ # ARM PrimeCell\r
+ #\r
+\r
+ ## SP805 Watchdog - Motherboard Watchdog\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
+ \r
+ ## PL011 - Serial Terminal\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1\r
+ gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32\r
+ gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|1000000\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
+\r
+ ## PL111 Versatile Express Motherboard controller\r
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
+ \r
+ #\r
+ # ARM PL390 General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
+\r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: \r
+ gArmTokenSpaceGuid.PcdArmMachineType|2272\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"NorFlash"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x46000000,0x46400000)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1\r
+\r
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
+\r
+ #\r
+ # ARM L2x0 PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000\r
+ \r
+ #\r
+ # ARM Architectual Timer Frequency\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|60000000\r
+ \r
+ \r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ \r
+ #\r
+ # SEC\r
+ #\r
+ ArmPlatformPkg/Sec/Sec.inf\r
+ \r
+ #\r
+ # PEI Phase modules\r
+ #\r
+!ifdef $(EDK2_SKIP_PEICORE)\r
+ ArmPlatformPkg/PrePi/PeiUniCore.inf {\r
+ <LibraryClasses>\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
+ }\r
+!else\r
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {\r
+ <LibraryClasses>\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
+ }\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ ArmPkg/Drivers/CpuPei/CpuPei.inf\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ Nt32Pkg/BootModePei/BootModePei.inf\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+!endif\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf \r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf \r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
+ \r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+ \r
+ #\r
+ # Multimedia Card Interface\r
+ #\r
+ EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
+ ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
+ \r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ FatPkg/EnhancedFatDxe/Fat.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Application\r
+ # \r
+ EmbeddedPkg/Ebl/Ebl.inf\r
+\r
+!ifdef $(EDK2_ARMVE_UEFI2_SHELL)\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <LibraryClasses>\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf\r
+\r
+ <PcdsFixedAtBuild>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000\r
+ }\r
+!endif\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ ArmPlatformPkg/Bds/Bds.inf\r
--- /dev/null
+# FLASH layout file for ARM VE.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.RTSM_VE_Cortex-A15_EFI]
+BaseAddress = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x280
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00080000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
+FV = FVMAIN_SEC
+
+0x00080000|0x00280000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvBaseSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
+ INF ShellPkg/Application/Shell/Shell.inf
+!endif
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+!else
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
--- /dev/null
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = ArmVExpressPkg-RTSM-A15_MPCore\r
+ PLATFORM_GUID = 3a91a0f8-3af4-409d-a71d-a199dc134357\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15_MPCore\r
+ SUPPORTED_ARCHITECTURES = ARM\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.fdf\r
+\r
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
+\r
+[LibraryClasses.common]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
+ \r
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
+ LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf\r
+\r
+ #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
+\r
+ # ARM PL390 General Interrupt Driver in Secure and Non-secure\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+\r
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf \r
+\r
+[LibraryClasses.common.SEC]\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressSecLib.inf\r
+[BuildOptions]\r
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+\r
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+ \r
+ XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag.common]\r
+!ifdef $(EDK2_SKIP_PEICORE)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE\r
+!endif\r
+ \r
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
+ # It could be set FALSE to save size.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ \r
+[PcdsFixedAtBuild.common]\r
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"\r
+ \r
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-RTSM"\r
+\r
+ #\r
+ # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
+\r
+ gArmTokenSpaceGuid.PcdVFPEnabled|1\r
+ \r
+ # Stacks for MPCores in Secure World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000\r
+ \r
+ # Stacks for MPCores in Monitor Mode\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100\r
+ \r
+ # Stacks for MPCores in Normal World\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000\r
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+ \r
+ # System Memory (1GB) \r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000\r
+ \r
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
+ \r
+ #\r
+ # ARM Pcds\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
+ \r
+ #\r
+ # ARM PrimeCell\r
+ #\r
+\r
+ ## SP805 Watchdog - Motherboard Watchdog\r
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
+ \r
+ ## PL011 - Serial Terminal\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1\r
+ gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32\r
+ gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|1000000\r
+\r
+ ## PL031 RealTimeClock\r
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
+\r
+ ## PL111 Versatile Express Motherboard controller\r
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
+ \r
+ #\r
+ # ARM PL390 General Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
+\r
+ #\r
+ # ARM OS Loader\r
+ #\r
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: \r
+ gArmTokenSpaceGuid.PcdArmMachineType|2272\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"NorFlash"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x46000000,0x46400000)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1\r
+\r
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
+\r
+ #\r
+ # ARM L2x0 PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000\r
+ \r
+ #\r
+ # ARM Architectual Timer Frequency\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|60000000\r
+ \r
+ \r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform\r
+#\r
+################################################################################\r
+[Components.common]\r
+ \r
+ #\r
+ # SEC\r
+ #\r
+ ArmPlatformPkg/Sec/Sec.inf\r
+ \r
+ #\r
+ # PEI Phase modules\r
+ #\r
+!ifdef $(EDK2_SKIP_PEICORE)\r
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
+ <LibraryClasses>\r
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf\r
+ }\r
+!else\r
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {\r
+ <LibraryClasses>\r
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf\r
+ }\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ ArmPkg/Drivers/CpuPei/CpuPei.inf\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ Nt32Pkg/BootModePei/BootModePei.inf\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+!endif\r
+\r
+ #\r
+ # DXE\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
+ }\r
+\r
+ #\r
+ # Architectural Protocols\r
+ #\r
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf \r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf \r
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ EmbeddedPkg/SerialDxe/SerialDxe.inf\r
+\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+\r
+ ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
+ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
+ \r
+ #\r
+ # Semi-hosting filesystem\r
+ #\r
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
+ \r
+ #\r
+ # Multimedia Card Interface\r
+ #\r
+ EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
+ ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
+ \r
+ #\r
+ # FAT filesystem + GPT/MBR partitioning\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ FatPkg/EnhancedFatDxe/Fat.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # Application\r
+ # \r
+ EmbeddedPkg/Ebl/Ebl.inf\r
+\r
+!ifdef $(EDK2_ARMVE_UEFI2_SHELL)\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <LibraryClasses>\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf\r
+\r
+ <PcdsFixedAtBuild>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000\r
+ }\r
+!endif\r
+\r
+ #\r
+ # Bds\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ ArmPlatformPkg/Bds/Bds.inf\r
--- /dev/null
+# FLASH layout file for ARM VE.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.RTSM_VE_Cortex-A15_MPCore_EFI]
+BaseAddress = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x280
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00080000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
+FV = FVMAIN_SEC
+
+0x00080000|0x00280000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvBaseSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
+ INF ShellPkg/Application/Shell/Shell.inf
+!endif
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+!else
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
\r
[Sources.common]\r
RTSM.c\r
- RTSMMem.c\r
+ RTSMMem.c \r
+ RTSMHelper.asm | RVCT\r
+ RTSMHelper.S | GCC\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
RTSM.c
RTSMBoot.asm | RVCT
RTSMBoot.S | GCC
+ RTSMHelper.asm | RVCT
+ RTSMHelper.S | GCC
[Protocols]
UINT32 ProcType;
ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
- if (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) {
+ if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
// Only support one cluster
*CoreCount = ArmGetCpuCountPerCluster ();
*ArmCoreTable = mVersatileExpressMpCoreInfoTable;
--- /dev/null
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http:#opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+#.include AsmMacroIoLib.inc\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
+\r
+# IN None\r
+# OUT r0 = SCU Base Address\r
+ASM_PFX(ArmGetScuBaseAddress):\r
+ # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ # offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+# IN None\r
+# OUT r0 = number of cores present in the system\r
+ASM_PFX(ArmGetCpuCountPerCluster):\r
+ stmfd SP!, {r1-r2}\r
+\r
+ # Read CP15 MIDR\r
+ mrc p15, 0, r1, c0, c0, 0\r
+\r
+ # Check if the CPU is A15\r
+ mov r1, r1, LSR #4\r
+ LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
+ and r1, r1, r0\r
+\r
+ LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
+ cmp r1, r0\r
+ beq _Read_cp15_reg\r
+\r
+_CPU_is_not_A15:\r
+ mov r2, lr @ Save link register\r
+ bl ArmGetScuBaseAddress @ Read SCU Base Address\r
+ mov lr, r2 @ Restore link register val\r
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
+ b _Return\r
+\r
+_Read_cp15_reg:\r
+ mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
+ lsr r0, #24\r
+\r
+_Return:\r
+ and r0, r0, #3\r
+ # Add '1' to the number of CPU on the Cluster\r
+ add r0, r0, #1\r
+ ldmfd SP!, {r1-r2}\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Chipset/ArmCortexA9.h>\r
+\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmGetCpuCountPerCluster\r
+ \r
+ AREA RTSMHelper, CODE, READONLY\r
+\r
+// IN None\r
+// OUT r0 = SCU Base Address\r
+ArmGetScuBaseAddress\r
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
+ // offset 0x0000 from the Private Memory Region.\r
+ mrc p15, 4, r0, c15, c0, 0\r
+ bx lr\r
+\r
+// IN None\r
+// OUT r0 = number of cores present in the system\r
+ArmGetCpuCountPerCluster\r
+ stmfd SP!, {r1-r2}\r
+\r
+ // Read CP15 MIDR\r
+ mrc p15, 0, r1, c0, c0, 0\r
+\r
+ // Check if the CPU is A15\r
+ mov r1, r1, LSR #4\r
+ mov r0, #ARM_CPU_TYPE_MASK\r
+ and r1, r1, r0\r
+\r
+ mov r0, #ARM_CPU_TYPE_A15\r
+ cmp r1, r0\r
+ beq _Read_cp15_reg\r
+\r
+_CPU_is_not_A15\r
+ mov r2, lr ; Save link register\r
+ bl ArmGetScuBaseAddress ; Read SCU Base Address\r
+ mov lr, r2 ; Restore link register val\r
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
+ b _Return\r
+\r
+_Read_cp15_reg\r
+ mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
+ lsr r0, #24\r
+\r
+\r
+_Return\r
+ and r0, r0, #3\r
+ // Add '1' to the number of CPU on the Cluster\r
+ add r0, r0, #1\r
+ ldmfd SP!, {r1-r2}\r
+ bx lr\r
+\r
+ END\r
projects / mirror_edk2.git / commitdiff