ArmPkg/ArmLib: Fixed AArch64 MMU code when a region overlaps 2 level-3 page tables

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15483 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index bababab880cb806c2cb0725ef531e3c94f1fc02c..fee4cfc4abc20f00f867abc1058abbbb4457c46e 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -397,8 +397,11 @@ GetBlockEntryListFromAddress (
         BlockEntry = TranslationTable;\r
       }\r
     } else {\r
-      // Case of Invalid Entry and we are at a page level above of the one targetted.\r
       if (IndexLevel != PageLevel) {\r
+        //\r
+        // Case when we have an Invalid Entry and we are at a page level above of the one targetted.\r
+        //\r
+\r
         // Create a new translation table\r
         TranslationTable = (UINT64*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE));\r
         if (TranslationTable == NULL) {\r
@@ -412,6 +415,11 @@ GetBlockEntryListFromAddress (
         *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;\r
         // Update the last block entry with the newly created translation table\r
         *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);\r
+      } else {\r
+        //\r
+        // Case when the new region is part of an existing page table\r
+        //\r
+        *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);\r
       }\r
     }\r
   }\r
@@ -531,8 +539,7 @@ ArmConfigureMmu (
   UINT64                        TCR;\r
   RETURN_STATUS                 Status;\r
 \r
-  if(MemoryTable == NULL)\r
-  {\r
+  if(MemoryTable == NULL) {\r
     ASSERT (MemoryTable != NULL);\r
     return RETURN_INVALID_PARAMETER;\r
   }\r