MdePkg/BaseSynchronizationLib: RISC-V cache related code.

Support RISC-V cache related functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63eb77df2c0816639d09e43bd622dade..83d5b8ed7c9b8c80f648b947f77a0b01074b3851 100755 (executable)
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
 #\r
 #  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
 #\r
 #  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -78,6 +79,10 @@
   AArch64/Synchronization.S     | GCC\r
   AArch64/Synchronization.asm   | MSFT\r
 \r
+[Sources.RISCV64]\r
+  Synchronization.c\r
+  RiscV64/Synchronization.S\r
+\r
 [Packages]\r
   MdePkg/MdePkg.dec\r
 \r

diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
new file mode 100644 (file)
index 0000000..bac80d6
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------\r
+//\r
+// RISC-V synchronization functions.\r
+//\r
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+#include <Base.h>\r
+\r
+.data\r
+\r
+.text\r
+.align 3\r
+\r
+.global ASM_PFX(InternalSyncCompareExchange32)\r
+.global ASM_PFX(InternalSyncCompareExchange64)\r
+.global ASM_PFX(InternalSyncIncrement)\r
+.global ASM_PFX(InternalSyncDecrement)\r
+\r
+//\r
+// ompare and xchange a 32-bit value.\r
+//\r
+// @param a0 : Pointer to 32-bit value.\r
+// @param a1 : Compare value.\r
+// @param a2 : Exchange value.\r
+//\r
+ASM_PFX (InternalSyncCompareExchange32):\r
+    lr.w  a3, (a0)        // Load the value from a0 and make\r
+                          // the reservation of address.\r
+    bne   a3, a1, exit\r
+    sc.w  a3, a2, (a0)    // Write the value back to the address.\r
+    mv    a3, a1\r
+exit:\r
+    mv    a0, a3\r
+    ret\r
+\r
+.global ASM_PFX(InternalSyncCompareExchange64)\r
+\r
+//\r
+// Compare and xchange a 64-bit value.\r
+//\r
+// @param a0 : Pointer to 64-bit value.\r
+// @param a1 : Compare value.\r
+// @param a2 : Exchange value.\r
+//\r
+ASM_PFX (SyncCompareExchange64):\r
+    lr.d  a3, (a0)       // Load the value from a0 and make\r
+                         // the reservation of address.\r
+    bne   a3, a1, exit\r
+    sc.d  a3, a2, (a0)   // Write the value back to the address.\r
+    mv    a3, a1\r
+exit2:\r
+    mv    a0, a3\r
+    ret\r
+\r
+//\r
+// Performs an atomic increment of an 32-bit unsigned integer.\r
+//\r
+// @param a0 : Pointer to 32-bit value.\r
+//\r
+ASM_PFX (InternalSyncIncrement):\r
+    li  a1, 1\r
+    amoadd.w  a2, a1, (a0)\r
+    mv  a0, a2\r
+    ret\r
+\r
+//\r
+// Performs an atomic decrement of an 32-bit unsigned integer.\r
+//\r
+// @param a0 : Pointer to 32-bit value.\r
+//\r
+ASM_PFX (InternalSyncDecrement):\r
+    li  a1, -1\r
+    amoadd.w  a2, a1, (a0)\r
+    mv  a0, a2\r
+    ret\r