]> git.proxmox.com Git - mirror_edk2.git/commitdiff
UefiCpuPkg/CpuCacheInfoLib: Correct logical for identifying cache type
authorJason <yun.lou@intel.com>
Fri, 13 Aug 2021 02:05:28 +0000 (10:05 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Mon, 23 Aug 2021 07:49:17 +0000 (07:49 +0000)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Correct the logical for identifying "Direct mapped" cache type.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c

index ae81ea9ce24d9ef923021bd48d25f0122b83591d..c0077d677000443652d23c31db8d146b09229e5b 100644 (file)
@@ -237,7 +237,7 @@ CpuCacheInfoCollectCoreAndCacheData (
     CacheData[CacheParamLeafIndex].CacheType             = (UINT8)CacheParamEax.Bits.CacheType;\r
     CacheData[CacheParamLeafIndex].CacheWays             = (UINT16)CacheParamEbx.Bits.Ways;\r
     CacheData[CacheParamLeafIndex].FullyAssociativeCache = (UINT8)CacheParamEax.Bits.FullyAssociativeCache;\r
-    CacheData[CacheParamLeafIndex].DirectMappedCache     = (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing;\r
+    CacheData[CacheParamLeafIndex].DirectMappedCache     = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0);\r
     CacheData[CacheParamLeafIndex].CacheShareBits        = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;\r
     CacheData[CacheParamLeafIndex].CacheSizeinKB         = (CacheParamEbx.Bits.Ways + 1) *\r
         (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;\r