Add register encoding definition for Memory Model Feature Register 2.
We need to define it here because we build for ARMv8.0, which doesn't
have it.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
#define ARM_VECTOR_LOW_A32_FIQ 0x700\r
#define ARM_VECTOR_LOW_A32_SERR 0x780\r
\r
+// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we\r
+// build for ARMv8.0, we need to define the register here.\r
+#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2\r
+\r
#define VECTOR_BASE(tbl) \\r
.section .text.##tbl##,"ax"; \\r
.align 11; \\r