--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# ArmReadIdIsar0() for AArch64\r
+#\r
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.p2align 2\r
+GCC_ASM_EXPORT(ArmReadIdIsar0)\r
+\r
+#/**\r
+# Reads the ID_AA64ISAR0 Register.\r
+#\r
+# @return The contents of the ID_AA64ISAR0 register.\r
+#\r
+#**/\r
+#UINT64\r
+#EFIAPI\r
+#ArmReadIdIsar0 (\r
+# VOID\r
+# );\r
+#\r
+ASM_PFX(ArmReadIdIsar0):\r
+ mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register\r
+ ret\r
+\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; ArmReadIdIsar0() for AArch64\r
+;\r
+; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+;\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT ArmReadIdIsar0\r
+ AREA BaseLib_LowLevel, CODE, READONLY\r
+\r
+;/**\r
+; Reads the ID_AA64ISAR0 Register.\r
+;\r
+; @return The contents of the ID_AA64ISAR0 register.\r
+;\r
+;**/\r
+;UINT64\r
+;EFIAPI\r
+;ArmReadIdIsar0 (\r
+; VOID\r
+; );\r
+;\r
+ArmReadIdIsar0\r
+ mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register\r
+ ret\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# ArmRndr() for AArch64\r
+#\r
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include "BaseRngLibInternals.h"\r
+\r
+.text\r
+.p2align 2\r
+GCC_ASM_EXPORT(ArmRndr)\r
+\r
+#/**\r
+# Generates a random number using RNDR.\r
+# Returns TRUE on success; FALSE on failure.\r
+#\r
+# @param[out] Rand Buffer pointer to store the 64-bit random value.\r
+#\r
+# @retval TRUE Random number generated successfully.\r
+# @retval FALSE Failed to generate the random number.\r
+#\r
+#**/\r
+#BOOLEAN\r
+#EFIAPI\r
+#ArmRndr (\r
+# OUT UINT64 *Rand\r
+# );\r
+#\r
+ASM_PFX(ArmRndr):\r
+ mrs x1, RNDR\r
+ str x1, [x0]\r
+ cset x0, ne // RNDR sets NZCV to 0b0100 on failure\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; ArmRndr() for AArch64\r
+;\r
+; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+;\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+#include "BaseRngLibInternals.h"\r
+\r
+ EXPORT ArmRndr\r
+ AREA BaseLib_LowLevel, CODE, READONLY\r
+\r
+\r
+;/**\r
+; Generates a random number using RNDR.\r
+; Returns TRUE on success; FALSE on failure.\r
+;\r
+; @param[out] Rand Buffer pointer to store the 64-bit random value.\r
+;\r
+; @retval TRUE Random number generated successfully.\r
+; @retval FALSE Failed to generate the random number.\r
+;\r
+;**/\r
+;BOOLEAN\r
+;EFIAPI\r
+;ArmRndr (\r
+; OUT UINT64 *Rand\r
+; );\r
+;\r
+ArmRndr\r
+ mrs x1, RNDR\r
+ str x1, [x0]\r
+ cset x0, ne // RNDR sets NZCV to 0b0100 on failure\r
+ ret\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ Random number generator service that uses the RNDR instruction\r
+ to provide pseudorandom numbers.\r
+\r
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef ARM_RNG_H_\r
+#define ARM_RNG_H_\r
+\r
+/**\r
+ Generates a random number using RNDR.\r
+ Returns TRUE on success; FALSE on failure.\r
+\r
+ @param[out] Rand Buffer pointer to store the 64-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArmRndr (\r
+ OUT UINT64 *Rand\r
+ );\r
+\r
+/**\r
+ Reads the ID_AA64ISAR0 Register.\r
+\r
+ @return The contents of the ID_AA64ISAR0 register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+ArmReadIdIsar0 (\r
+ VOID\r
+ );\r
+\r
+#endif /* ARM_RNG_H_ */\r
--- /dev/null
+/** @file\r
+ Random number generator service that uses the RNDR instruction\r
+ to provide pseudorandom numbers.\r
+\r
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/RngLib.h>\r
+\r
+#include "ArmRng.h"\r
+#include "BaseRngLibInternals.h"\r
+\r
+STATIC BOOLEAN mRndrSupported;\r
+\r
+//\r
+// Bit mask used to determine if RNDR instruction is supported.\r
+//\r
+#define RNDR_MASK ((UINT64)MAX_UINT16 << 60U)\r
+\r
+/**\r
+ The constructor function checks whether or not RNDR instruction is supported\r
+ by the host hardware.\r
+\r
+ The constructor function checks whether or not RNDR instruction is supported.\r
+ It will ASSERT() if RNDR instruction is not supported.\r
+ It will always return EFI_SUCCESS.\r
+\r
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BaseRngLibConstructor (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Isar0;\r
+ //\r
+ // Determine RNDR support by examining bits 63:60 of the ISAR0 register returned by\r
+ // MSR. A non-zero value indicates that the processor supports the RNDR instruction.\r
+ //\r
+ Isar0 = ArmReadIdIsar0 ();\r
+ ASSERT ((Isar0 & RNDR_MASK) != 0);\r
+\r
+ mRndrSupported = ((Isar0 & RNDR_MASK) != 0);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Generates a 16-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 16-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber16 (\r
+ OUT UINT16 *Rand\r
+ )\r
+{\r
+ UINT64 Rand64;\r
+\r
+ if (ArchGetRandomNumber64 (&Rand64)) {\r
+ *Rand = Rand64 & MAX_UINT16;\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Generates a 32-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 32-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber32 (\r
+ OUT UINT32 *Rand\r
+ )\r
+{\r
+ UINT64 Rand64;\r
+\r
+ if (ArchGetRandomNumber64 (&Rand64)) {\r
+ *Rand = Rand64 & MAX_UINT32;\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Generates a 64-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 64-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber64 (\r
+ OUT UINT64 *Rand\r
+ )\r
+{\r
+ return ArmRndr (Rand);\r
+}\r
+\r
+/**\r
+ Checks whether RNDR is supported.\r
+\r
+ @retval TRUE RNDR is supported.\r
+ @retval FALSE RNDR is not supported.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchIsRngSupported (\r
+ VOID\r
+ )\r
+{\r
+ return mRndrSupported;\r
+}\r
/** @file\r
- Random number generator services that uses RdRand instruction access\r
- to provide high-quality random numbers.\r
+ Random number generator services that uses CPU RNG instructions to\r
+ provide random numbers.\r
\r
+Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
\r
-//\r
-// Bit mask used to determine if RdRand instruction is supported.\r
-//\r
-#define RDRAND_MASK BIT30\r
+#include "BaseRngLibInternals.h"\r
\r
//\r
// Limited retry number when valid random data is returned.\r
// Uses the recommended value defined in Section 7.3.17 of "Intel 64 and IA-32\r
-// Architectures Software Developer's Mannual".\r
+// Architectures Software Developer's Manual".\r
//\r
-#define RDRAND_RETRY_LIMIT 10\r
-\r
-/**\r
- The constructor function checks whether or not RDRAND instruction is supported\r
- by the host hardware.\r
-\r
- The constructor function checks whether or not RDRAND instruction is supported.\r
- It will ASSERT() if RDRAND instruction is not supported.\r
- It will always return RETURN_SUCCESS.\r
-\r
- @retval RETURN_SUCCESS The constructor always returns EFI_SUCCESS.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-BaseRngLibConstructor (\r
- VOID\r
- )\r
-{\r
- UINT32 RegEcx;\r
-\r
- //\r
- // Determine RDRAND support by examining bit 30 of the ECX register returned by\r
- // CPUID. A value of 1 indicates that processor support RDRAND instruction.\r
- //\r
- AsmCpuid (1, 0, 0, &RegEcx, 0);\r
- ASSERT ((RegEcx & RDRAND_MASK) == RDRAND_MASK);\r
+#define GETRANDOM_RETRY_LIMIT 10\r
\r
- return RETURN_SUCCESS;\r
-}\r
\r
/**\r
Generates a 16-bit random number.\r
\r
ASSERT (Rand != NULL);\r
\r
+ if (Rand == NULL) {\r
+ return FALSE;\r
+ }\r
+\r
+ if (!ArchIsRngSupported ()) {\r
+ return FALSE;\r
+ }\r
+\r
//\r
// A loop to fetch a 16 bit random value with a retry count limit.\r
//\r
- for (Index = 0; Index < RDRAND_RETRY_LIMIT; Index++) {\r
- if (AsmRdRand16 (Rand)) {\r
+ for (Index = 0; Index < GETRANDOM_RETRY_LIMIT; Index++) {\r
+ if (ArchGetRandomNumber16 (Rand)) {\r
return TRUE;\r
}\r
}\r
\r
ASSERT (Rand != NULL);\r
\r
+ if (Rand == NULL) {\r
+ return FALSE;\r
+ }\r
+\r
+ if (!ArchIsRngSupported ()) {\r
+ return FALSE;\r
+ }\r
+\r
//\r
// A loop to fetch a 32 bit random value with a retry count limit.\r
//\r
- for (Index = 0; Index < RDRAND_RETRY_LIMIT; Index++) {\r
- if (AsmRdRand32 (Rand)) {\r
+ for (Index = 0; Index < GETRANDOM_RETRY_LIMIT; Index++) {\r
+ if (ArchGetRandomNumber32 (Rand)) {\r
return TRUE;\r
}\r
}\r
\r
ASSERT (Rand != NULL);\r
\r
+ if (Rand == NULL) {\r
+ return FALSE;\r
+ }\r
+\r
+ if (!ArchIsRngSupported ()) {\r
+ return FALSE;\r
+ }\r
+\r
//\r
// A loop to fetch a 64 bit random value with a retry count limit.\r
//\r
- for (Index = 0; Index < RDRAND_RETRY_LIMIT; Index++) {\r
- if (AsmRdRand64 (Rand)) {\r
+ for (Index = 0; Index < GETRANDOM_RETRY_LIMIT; Index++) {\r
+ if (ArchGetRandomNumber64 (Rand)) {\r
return TRUE;\r
}\r
}\r
{\r
ASSERT (Rand != NULL);\r
\r
+ if (Rand == NULL) {\r
+ return FALSE;\r
+ }\r
+\r
+ if (!ArchIsRngSupported ()) {\r
+ return FALSE;\r
+ }\r
+\r
//\r
// Read first 64 bits\r
//\r
## @file\r
# Instance of RNG (Random Number Generator) Library.\r
#\r
-# BaseRng Library that uses CPU RdRand instruction access to provide\r
-# high-quality random numbers.\r
+# BaseRng Library that uses CPU RNG instructions (e.g. RdRand) to\r
+# provide random numbers.\r
#\r
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
CONSTRUCTOR = BaseRngLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64\r
+# VALID_ARCHITECTURES = IA32 X64 AARCH64\r
#\r
\r
-[Sources.Ia32, Sources.X64]\r
+[Sources]\r
BaseRng.c\r
+ BaseRngLibInternals.h\r
+\r
+[Sources.Ia32, Sources.X64]\r
+ Rand/RdRand.c\r
+\r
+[Sources.AARCH64]\r
+ AArch64/Rndr.c\r
+ AArch64/ArmRng.h\r
+\r
+ AArch64/ArmReadIdIsar0.S | GCC\r
+ AArch64/ArmRng.S | GCC\r
+\r
+ AArch64/ArmReadIdIsar0.asm | MSFT\r
+ AArch64/ArmRng.asm | MSFT\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
// /** @file\r
// Instance of RNG (Random Number Generator) Library.\r
//\r
-// BaseRng Library that uses CPU RdRand instruction access to provide\r
-// high-quality random numbers.\r
+// BaseRng Library that uses CPU RNG instructions to provide\r
+// random numbers.\r
//\r
// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
//\r
\r
#string STR_MODULE_ABSTRACT #language en-US "Instance of RNG Library"\r
\r
-#string STR_MODULE_DESCRIPTION #language en-US "BaseRng Library that uses CPU RdRand instruction access to provide high-quality random numbers"\r
-\r
+#string STR_MODULE_DESCRIPTION #language en-US "BaseRng Library that uses CPU RNG instructions to provide random numbers"\r
--- /dev/null
+/** @file\r
+\r
+ Architecture specific interface to RNG functionality.\r
+\r
+Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef BASE_RNGLIB_INTERNALS_H_\r
+\r
+/**\r
+ Generates a 16-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 16-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber16 (\r
+ OUT UINT16 *Rand\r
+ );\r
+\r
+/**\r
+ Generates a 32-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 32-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber32 (\r
+ OUT UINT32 *Rand\r
+ );\r
+\r
+/**\r
+ Generates a 64-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 64-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber64 (\r
+ OUT UINT64 *Rand\r
+ );\r
+\r
+/**\r
+ Checks whether the RNG instruction is supported.\r
+\r
+ @retval TRUE RNG instruction is supported.\r
+ @retval FALSE RNG instruction is not supported.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchIsRngSupported (\r
+ VOID\r
+ );\r
+\r
+#if defined (MDE_CPU_AARCH64)\r
+\r
+// RNDR, Random Number\r
+#define RNDR S3_3_C2_C4_0\r
+\r
+#endif\r
+\r
+#endif // BASE_RNGLIB_INTERNALS_H_\r
--- /dev/null
+/** @file\r
+ Random number generator services that uses RdRand instruction access\r
+ to provide high-quality random numbers.\r
+\r
+Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include "BaseRngLibInternals.h"\r
+\r
+//\r
+// Bit mask used to determine if RdRand instruction is supported.\r
+//\r
+#define RDRAND_MASK BIT30\r
+\r
+\r
+STATIC BOOLEAN mRdRandSupported;\r
+\r
+/**\r
+ The constructor function checks whether or not RDRAND instruction is supported\r
+ by the host hardware.\r
+\r
+ The constructor function checks whether or not RDRAND instruction is supported.\r
+ It will ASSERT() if RDRAND instruction is not supported.\r
+ It will always return EFI_SUCCESS.\r
+\r
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BaseRngLibConstructor (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEcx;\r
+\r
+ //\r
+ // Determine RDRAND support by examining bit 30 of the ECX register returned by\r
+ // CPUID. A value of 1 indicates that processor support RDRAND instruction.\r
+ //\r
+ AsmCpuid (1, 0, 0, &RegEcx, 0);\r
+ ASSERT ((RegEcx & RDRAND_MASK) == RDRAND_MASK);\r
+\r
+ mRdRandSupported = ((RegEcx & RDRAND_MASK) == RDRAND_MASK);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Generates a 16-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 16-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber16 (\r
+ OUT UINT16 *Rand\r
+ )\r
+{\r
+ return AsmRdRand16 (Rand);\r
+}\r
+\r
+/**\r
+ Generates a 32-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 32-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber32 (\r
+ OUT UINT32 *Rand\r
+ )\r
+{\r
+ return AsmRdRand32 (Rand);\r
+}\r
+\r
+/**\r
+ Generates a 64-bit random number.\r
+\r
+ @param[out] Rand Buffer pointer to store the 64-bit random value.\r
+\r
+ @retval TRUE Random number generated successfully.\r
+ @retval FALSE Failed to generate the random number.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchGetRandomNumber64 (\r
+ OUT UINT64 *Rand\r
+ )\r
+{\r
+ return AsmRdRand64 (Rand);\r
+}\r
+\r
+/**\r
+ Checks whether RDRAND is supported.\r
+\r
+ @retval TRUE RDRAND is supported.\r
+ @retval FALSE RDRAND is not supported.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+ArchIsRngSupported (\r
+ VOID\r
+ )\r
+{\r
+ /*\r
+ Existing software depends on this always returning TRUE, so for\r
+ now hard-code it.\r
+\r
+ return mRdRandSupported;\r
+ */\r
+ return TRUE;\r
+}\r
#\r
RegisterFilterLib|Include/Library/RegisterFilterLib.h\r
\r
+[LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64]\r
+ ## @libraryclass Provides services to generate random number.\r
+ #\r
+ RngLib|Include/Library/RngLib.h\r
+\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
## @libraryclass Abstracts both S/W SMI generation and detection.\r
##\r
#\r
SmmPeriodicSmiLib|Include/Library/SmmPeriodicSmiLib.h\r
\r
- ## @libraryclass Provides services to generate random number.\r
- #\r
- RngLib|Include/Library/RngLib.h\r
-\r
## @libraryclass Provides services to log the SMI handler registration.\r
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h\r
\r
MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf\r
MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf\r
\r
+[Components.IA32, Components.X64, Components.AARCH64]\r
+ MdePkg/Library/BaseRngLib/BaseRngLib.inf\r
+\r
[Components.IA32, Components.X64]\r
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf\r
MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf\r
MdePkg/Library/SmmMemLib/SmmMemLib.inf\r
MdePkg/Library/SmmIoLib/SmmIoLib.inf\r
- MdePkg/Library/BaseRngLib/BaseRngLib.inf\r
MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf\r
MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf\r
MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf\r