--- /dev/null
+/** @file\r
+ Basic TIS (TPM Interface Specification) functions for Infineon I2C TPM.\r
+\r
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/Tpm12DeviceLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/I2cLib.h>\r
+\r
+//\r
+// Default TPM (Infineon SLB9645) I2C Slave Device Address on Crosshill board.\r
+//\r
+#define TPM_I2C_SLAVE_DEVICE_ADDRESS 0x20\r
+\r
+//\r
+// Default Infineon SLB9645 TPM I2C mapped registers (SLB9645 I2C Comm. Protocol Application Note).\r
+//\r
+#define INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT 0x0\r
+#define INFINEON_TPM_STS_0_ADDRESS_DEFAULT 0x01\r
+#define INFINEON_TPM_BURST0_COUNT_0_DEFAULT 0x02\r
+#define INFINEON_TPM_BURST1_COUNT_0_DEFAULT 0x03\r
+#define INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT 0x05\r
+#define INFINEON_TPM_DID_VID_0_DEFAULT 0x09\r
+\r
+//\r
+// Max. retry count for read transfers (as recommended by Infineon).\r
+//\r
+#define READ_RETRY 3\r
+\r
+//\r
+// Guard time of 250us between I2C read and next I2C write transfer (as recommended by Infineon).\r
+//\r
+#define GUARD_TIME 250\r
+\r
+//\r
+// Define bits of ACCESS and STATUS registers\r
+//\r
+\r
+///\r
+/// This bit is a 1 to indicate that the other bits in this register are valid.\r
+///\r
+#define TIS_PC_VALID BIT7\r
+///\r
+/// Indicate that this locality is active.\r
+///\r
+#define TIS_PC_ACC_ACTIVE BIT5\r
+///\r
+/// Set to 1 to indicate that this locality had the TPM taken away while\r
+/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
+///\r
+#define TIS_PC_ACC_SEIZED BIT4\r
+///\r
+/// Set to 1 to indicate that TPM MUST reset the\r
+/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
+/// locality that is writing this bit.\r
+///\r
+#define TIS_PC_ACC_SEIZE BIT3\r
+///\r
+/// When this bit is 1, another locality is requesting usage of the TPM.\r
+///\r
+#define TIS_PC_ACC_PENDIND BIT2\r
+///\r
+/// Set to 1 to indicate that this locality is requesting to use TPM.\r
+///\r
+#define TIS_PC_ACC_RQUUSE BIT1\r
+///\r
+/// A value of 1 indicates that a T/OS has not been established on the platform\r
+///\r
+#define TIS_PC_ACC_ESTABLISH BIT0\r
+\r
+///\r
+/// When this bit is 1, TPM is in the Ready state,\r
+/// indicating it is ready to receive a new command.\r
+///\r
+#define TIS_PC_STS_READY BIT6\r
+///\r
+/// Write a 1 to this bit to cause the TPM to execute that command.\r
+///\r
+#define TIS_PC_STS_GO BIT5\r
+///\r
+/// This bit indicates that the TPM has data available as a response.\r
+///\r
+#define TIS_PC_STS_DATA BIT4\r
+///\r
+/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
+///\r
+#define TIS_PC_STS_EXPECT BIT3\r
+///\r
+/// Writes a 1 to this bit to force the TPM to re-send the response.\r
+///\r
+#define TIS_PC_STS_RETRY BIT1\r
+\r
+//\r
+// Default TimeOut values in microseconds\r
+//\r
+#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
+#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
+\r
+//\r
+// Global variable to indicate if TPM I2C Read Transfer has previously occurred.\r
+// NOTE: Given the GUARD_TIME requirement (TpmAccess.h), if this library loaded\r
+// by PEI Drivers this global variable required to be resident in R/W memory\r
+//\r
+BOOLEAN mI2CPrevReadTransfer = FALSE;\r
+\r
+/**\r
+ Writes single byte data to TPM specified by I2C register address.\r
+\r
+ @param[in] TpmAddress The register to write.\r
+ @param[in] Data The data to write to the register.\r
+\r
+**/\r
+VOID\r
+TpmWriteByte (\r
+ IN UINTN TpmAddress,\r
+ IN UINT8 Data\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN WriteLength;\r
+ UINT8 WriteData[2];\r
+ EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr;\r
+\r
+ //\r
+ // Setup I2C Slave device address and address mode (7-bit).\r
+ //\r
+ I2CDeviceAddr.I2CDeviceAddress = TPM_I2C_SLAVE_DEVICE_ADDRESS;\r
+\r
+ //\r
+ // As recommended by Infineon (SLB9645 I2C Communication protocol application\r
+ // note revision 1.0) wait 250 microseconds between a read and a write transfer.\r
+ //\r
+ if (mI2CPrevReadTransfer) {\r
+ MicroSecondDelay (GUARD_TIME);\r
+ }\r
+\r
+ //\r
+ // Write to TPM register.\r
+ //\r
+ WriteLength = 2;\r
+ WriteData[0] = (UINT8)TpmAddress;\r
+ WriteData[1] = Data;\r
+\r
+ Status = I2cWriteMultipleByte (\r
+ I2CDeviceAddr,\r
+ EfiI2CSevenBitAddrMode,\r
+ &WriteLength,\r
+ &WriteData\r
+ );\r
+ if (EFI_ERROR(Status)) {\r
+ DEBUG ((EFI_D_ERROR, "TpmWriteByte(): I2C Write to TPM address %0x failed (%r)\n", TpmAddress, Status));\r
+ ASSERT (FALSE); // Writes to TPM should always succeed.\r
+ }\r
+\r
+ mI2CPrevReadTransfer = FALSE;\r
+}\r
+\r
+/**\r
+ Reads single byte data from TPM specified by I2C register address.\r
+\r
+ Due to stability issues when using I2C combined write/read transfers (with\r
+ RESTART) to TPM (specifically read from status register), a single write is\r
+ performed followed by single read (with STOP condition in between).\r
+\r
+ @param[in] TpmAddress Address of register to read.\r
+\r
+ @return The value register read.\r
+\r
+**/\r
+UINT8\r
+TpmReadByte (\r
+ IN UINTN TpmAddress\r
+ )\r
+{\r
+ UINT8 Data[1];\r
+ UINT8 ReadData;\r
+ UINT8 ReadCount;\r
+\r
+ EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr;\r
+ EFI_I2C_ADDR_MODE I2CAddrMode;\r
+\r
+ EFI_STATUS Status;\r
+\r
+ Status = EFI_SUCCESS;\r
+ ReadData = 0xFF;\r
+ ReadCount = 0;\r
+\r
+ //\r
+ // Locate I2C protocol for TPM I2C access.\r
+ //\r
+ I2CDeviceAddr.I2CDeviceAddress = TPM_I2C_SLAVE_DEVICE_ADDRESS;\r
+ I2CAddrMode = EfiI2CSevenBitAddrMode;\r
+\r
+ //\r
+ // As recommended by Infineon (SLB9645 I2C Communication protocol application\r
+ // note revision 1.0) retry up to 3 times if TPM status, access or burst count\r
+ // registers return 0xFF.\r
+ //\r
+ while ((ReadData == 0xFF) && (ReadCount < READ_RETRY)) {\r
+ //\r
+ // As recommended by Infineon (SLB9645 I2C Communication protocol application\r
+ // note revision 1.0) wait 250 microseconds between a read and a write transfer.\r
+ //\r
+ if (mI2CPrevReadTransfer) {\r
+ MicroSecondDelay (GUARD_TIME);\r
+ }\r
+\r
+ //\r
+ // Write address to TPM.\r
+ //\r
+ Data[0] = (UINT8)TpmAddress;\r
+ Status = I2cWriteByte (\r
+ I2CDeviceAddr,\r
+ I2CAddrMode,\r
+ &Data\r
+ );\r
+\r
+ if (EFI_ERROR(Status)) {\r
+ DEBUG ((EFI_D_INFO, "TpmReadByte(): write to TPM address %0x failed (%r)\n", TpmAddress, Status));\r
+ }\r
+\r
+ mI2CPrevReadTransfer = FALSE;\r
+\r
+ //\r
+ // Read data from TPM.\r
+ //\r
+ Data[0] = (UINT8)TpmAddress;\r
+ Status = I2cReadByte (\r
+ I2CDeviceAddr,\r
+ I2CAddrMode,\r
+ &Data\r
+ );\r
+\r
+ if (EFI_ERROR(Status)) {\r
+ DEBUG ((EFI_D_INFO, "TpmReadByte(): read from TPM address %0x failed (%r)\n", TpmAddress, Status));\r
+ ReadData = 0xFF;\r
+ } else {\r
+ ReadData = Data[0];\r
+ }\r
+\r
+ //\r
+ // Only need to retry 3 times for TPM status, access, and burst count registers.\r
+ // If read transfer is to TPM Data FIFO, do not retry, exit loop.\r
+ //\r
+ if (TpmAddress == INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT) {\r
+ ReadCount = READ_RETRY;\r
+ } else {\r
+ ReadCount++;\r
+ }\r
+\r
+ mI2CPrevReadTransfer = TRUE;\r
+ }\r
+\r
+ if (EFI_ERROR(Status)) {\r
+ //\r
+ // Only reads to access register allowed to fail.\r
+ //\r
+ if (TpmAddress != INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT) {\r
+ DEBUG ((EFI_D_ERROR, "TpmReadByte(): read from TPM address %0x failed\n", TpmAddress));\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ }\r
+ return ReadData;\r
+}\r
+\r
+/**\r
+ Check whether the value of a TPM chip register satisfies the input BIT setting.\r
+\r
+ @param[in] Register TPM register to be checked.\r
+ @param[in] BitSet Check these data bits are set.\r
+ @param[in] BitClear Check these data bits are clear.\r
+ @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
+\r
+ @retval EFI_SUCCESS The register satisfies the check bit.\r
+ @retval EFI_TIMEOUT The register can't run into the expected status in time.\r
+**/\r
+EFI_STATUS\r
+TisPcWaitRegisterBits (\r
+ IN UINTN Register,\r
+ IN UINT8 BitSet,\r
+ IN UINT8 BitClear,\r
+ IN UINT32 TimeOut\r
+ )\r
+{\r
+ UINT8 RegRead;\r
+ UINT32 WaitTime;\r
+\r
+ for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
+ RegRead = TpmReadByte (Register);\r
+ if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
+ return EFI_SUCCESS;\r
+ MicroSecondDelay (30);\r
+ }\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+/**\r
+ Get BurstCount by reading the burstCount field of a TIS register\r
+ in the time of default TIS_TIMEOUT_D.\r
+\r
+ @param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r
+\r
+ @retval EFI_SUCCESS Get BurstCount.\r
+ @retval EFI_INVALID_PARAMETER BurstCount is NULL.\r
+ @retval EFI_TIMEOUT BurstCount can't be got in time.\r
+**/\r
+EFI_STATUS\r
+TisPcReadBurstCount (\r
+ OUT UINT16 *BurstCount\r
+ )\r
+{\r
+ UINT32 WaitTime;\r
+ UINT8 DataByte0;\r
+ UINT8 DataByte1;\r
+\r
+ if (BurstCount == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ WaitTime = 0;\r
+ do {\r
+ //\r
+ // BurstCount is UINT16, but it is not 2bytes aligned,\r
+ // so it needs to use TpmReadByte to read two times\r
+ //\r
+ DataByte0 = TpmReadByte (INFINEON_TPM_BURST0_COUNT_0_DEFAULT);\r
+ DataByte1 = TpmReadByte (INFINEON_TPM_BURST1_COUNT_0_DEFAULT);\r
+ *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
+ if (*BurstCount != 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ MicroSecondDelay (30);\r
+ WaitTime += 30;\r
+ } while (WaitTime < TIS_TIMEOUT_D);\r
+\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+/**\r
+ Set TPM chip to ready state by sending ready command TIS_PC_STS_READY\r
+ to Status Register in time.\r
+\r
+ @retval EFI_SUCCESS TPM chip enters into ready state.\r
+ @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r
+**/\r
+EFI_STATUS\r
+TisPcPrepareCommand (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_READY);\r
+ Status = TisPcWaitRegisterBits (\r
+ INFINEON_TPM_STS_0_ADDRESS_DEFAULT,\r
+ TIS_PC_STS_READY,\r
+ 0,\r
+ TIS_TIMEOUT_B\r
+ );\r
+ return Status;\r
+}\r
+\r
+/**\r
+ This service requests use TPM12.\r
+\r
+ @retval EFI_SUCCESS Get the control of TPM12 chip.\r
+ @retval EFI_NOT_FOUND TPM12 not found.\r
+ @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Tpm12RequestUseTpm (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Check to see if TPM exists\r
+ //\r
+ if (TpmReadByte (INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT) == 0xFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ TpmWriteByte (INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT, TIS_PC_ACC_RQUUSE);\r
+\r
+ //\r
+ // No locality set before, ACCESS_X.activeLocality MUST be valid within TIMEOUT_A\r
+ //\r
+ Status = TisPcWaitRegisterBits (\r
+ INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT,\r
+ (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r
+ 0,\r
+ TIS_TIMEOUT_A\r
+ );\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Send command to TPM for execution.\r
+\r
+ @param[in] TpmBuffer Buffer for TPM command data.\r
+ @param[in] DataLength TPM command data length.\r
+\r
+ @retval EFI_SUCCESS Operation completed successfully.\r
+ @retval EFI_TIMEOUT The register can't run into the expected status in time.\r
+\r
+**/\r
+EFI_STATUS\r
+TisPcSend (\r
+ IN UINT8 *TpmBuffer,\r
+ IN UINT32 DataLength\r
+ )\r
+{\r
+ UINT16 BurstCount;\r
+ UINT32 Index;\r
+ EFI_STATUS Status;\r
+\r
+ Status = TisPcPrepareCommand ();\r
+ if (EFI_ERROR (Status)){\r
+ DEBUG ((DEBUG_ERROR, "The TPM is not ready!\n"));\r
+ goto Done;\r
+ }\r
+ Index = 0;\r
+ while (Index < DataLength) {\r
+ Status = TisPcReadBurstCount (&BurstCount);\r
+ if (EFI_ERROR (Status)) {\r
+ Status = EFI_TIMEOUT;\r
+ goto Done;\r
+ }\r
+ for (; BurstCount > 0 && Index < DataLength; BurstCount--) {\r
+ TpmWriteByte (INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT, *(TpmBuffer + Index));\r
+ Index++;\r
+ }\r
+ }\r
+ //\r
+ // Ensure the TPM status STS_EXPECT change from 1 to 0\r
+ //\r
+ Status = TisPcWaitRegisterBits (\r
+ INFINEON_TPM_STS_0_ADDRESS_DEFAULT,\r
+ (UINT8) TIS_PC_VALID,\r
+ TIS_PC_STS_EXPECT,\r
+ TIS_TIMEOUT_C\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ goto Done;\r
+ }\r
+\r
+ //\r
+ // Start the command\r
+ //\r
+ TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_GO);\r
+\r
+Done:\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Ensure the TPM state change from "Reception" to "Idle/Ready"\r
+ //\r
+ TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_READY);\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Receive response data of last command from TPM.\r
+\r
+ @param[out] TpmBuffer Buffer for response data.\r
+ @param[out] RespSize Response data length.\r
+\r
+ @retval EFI_SUCCESS Operation completed successfully.\r
+ @retval EFI_TIMEOUT The register can't run into the expected status in time.\r
+ @retval EFI_DEVICE_ERROR Unexpected device status.\r
+ @retval EFI_BUFFER_TOO_SMALL Response data is too long.\r
+\r
+**/\r
+EFI_STATUS\r
+TisPcReceive (\r
+ OUT UINT8 *TpmBuffer,\r
+ OUT UINT32 *RespSize\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT16 BurstCount;\r
+ UINT32 Index;\r
+ UINT32 ResponseSize;\r
+ TPM_RSP_COMMAND_HDR *ResponseHeader;\r
+\r
+ //\r
+ // Wait for the command completion\r
+ //\r
+ Status = TisPcWaitRegisterBits (\r
+ INFINEON_TPM_STS_0_ADDRESS_DEFAULT,\r
+ (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r
+ 0,\r
+ TIS_TIMEOUT_B\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ Status = EFI_TIMEOUT;\r
+ goto Done;\r
+ }\r
+ //\r
+ // Read the response data header and check it\r
+ //\r
+ Index = 0;\r
+ BurstCount = 0;\r
+ while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r
+ Status = TisPcReadBurstCount (&BurstCount);\r
+ if (EFI_ERROR (Status)) {\r
+ Status = EFI_TIMEOUT;\r
+ goto Done;\r
+ }\r
+ for (; BurstCount > 0 ; BurstCount--) {\r
+ *(TpmBuffer + Index) = TpmReadByte (INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT);\r
+ Index++;\r
+ if (Index == sizeof (TPM_RSP_COMMAND_HDR))\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Check the response data header (tag, parasize and returncode)\r
+ //\r
+ ResponseHeader = (TPM_RSP_COMMAND_HDR *)TpmBuffer;\r
+ if (SwapBytes16 (ReadUnaligned16 (&ResponseHeader->tag)) != TPM_TAG_RSP_COMMAND) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ goto Done;\r
+ }\r
+\r
+ ResponseSize = SwapBytes32 (ReadUnaligned32 (&ResponseHeader->paramSize));\r
+ if (ResponseSize == sizeof (TPM_RSP_COMMAND_HDR)) {\r
+ Status = EFI_SUCCESS;\r
+ goto Done;\r
+ }\r
+ if (ResponseSize < sizeof (TPM_RSP_COMMAND_HDR)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ goto Done;\r
+ }\r
+ if (*RespSize < ResponseSize) {\r
+ Status = EFI_BUFFER_TOO_SMALL;\r
+ goto Done;\r
+ }\r
+ *RespSize = ResponseSize;\r
+\r
+ //\r
+ // Continue reading the remaining data\r
+ //\r
+ while (Index < ResponseSize) {\r
+ for (; BurstCount > 0 ; BurstCount--) {\r
+ *(TpmBuffer + Index) = TpmReadByte (INFINEON_TPM_DATA_FIFO_0_ADDRESS_DEFAULT);\r
+ Index++;\r
+ if (Index == ResponseSize) {\r
+ Status = EFI_SUCCESS;\r
+ goto Done;\r
+ }\r
+ }\r
+ Status = TisPcReadBurstCount (&BurstCount);\r
+ if (EFI_ERROR (Status) && (Index < ResponseSize)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ goto Done;\r
+ }\r
+ }\r
+\r
+Done:\r
+ //\r
+ // Ensure the TPM state change from "Execution" or "Completion" to "Idle/Ready"\r
+ //\r
+ TpmWriteByte (INFINEON_TPM_STS_0_ADDRESS_DEFAULT, TIS_PC_STS_READY);\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ This service enables the sending of commands to the TPM12.\r
+\r
+ @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.\r
+ @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.\r
+ @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.\r
+ @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.\r
+\r
+ @retval EFI_SUCCESS The command byte stream was successfully sent to\r
+ the device and a response was successfully received.\r
+ @retval EFI_DEVICE_ERROR The command was not successfully sent to the\r
+ device or a response was not successfully received\r
+ from the device.\r
+ @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Tpm12SubmitCommand (\r
+ IN UINT32 InputParameterBlockSize,\r
+ IN UINT8 *InputParameterBlock,\r
+ IN OUT UINT32 *OutputParameterBlockSize,\r
+ IN UINT8 *OutputParameterBlock\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = TisPcSend (InputParameterBlock, InputParameterBlockSize);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = TisPcReceive (OutputParameterBlock, OutputParameterBlockSize);\r
+ }\r
+ return Status;\r
+}\r
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