Add Add ARM support

Add C inline assembly files for IA32 and X64 GCC builds.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9114 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
new file mode 100644 (file)
index 0000000..6581425
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------ \r
+#\r
+# CpuFlushTlb() for ARM\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.p2align 2\r
+.globl ASM_PFX(CpuFlushTlb)\r
+\r
+#/**\r
+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+#\r
+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#CpuFlushTlb (\r
+#  VOID\r
+#  )#\r
+#\r
+ASM_PFX(CpuFlushTlb):\r
+    mov r0,#0\r
+    mcr p15,0,r0,c8,c5,0        # Invalidate all the unlocked entried in TLB\r
+    bx  LR\r

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
new file mode 100644 (file)
index 0000000..e0ccdfd
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ \r
+;\r
+; CpuFlushTlb() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+  EXPORT CpuFlushTlb\r
+  AREA cpu_flush_tlb, CODE, READONLY\r
+\r
+;/**\r
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+;\r
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;CpuFlushTlb (\r
+;  VOID\r
+;  );\r
+;\r
+CpuFlushTlb \r
+    MOV r0,#0\r
+    MCR p15,0,r0,c8,c5,0        ;Invalidate all the unlocked entried in TLB\r
+    BX LR\r
+\r
+  END\r

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
new file mode 100644 (file)
index 0000000..8d06372
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------ \r
+#\r
+# CpuSleep() for ARM\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.p2align 2\r
+.globl ASM_PFX(CpuSleep)\r
+\r
+#/**\r
+#  Places the CPU in a sleep state until an interrupt is received.\r
+#\r
+#  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+#  are disabled prior to calling this function, then the CPU will be placed in a\r
+#  sleep state indefinitely.\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#CpuSleep (\r
+#  VOID\r
+#  );\r
+#\r
+ASM_PFX(CpuSleep):\r
+    mov r0,#0\r
+    mcr p15,0,r0,c7,c0,4   ;Wait for Interrupt instruction\r
+    bx  lr\r

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
new file mode 100644 (file)
index 0000000..e0aaf21
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
@@ -0,0 +1,39 @@
+;------------------------------------------------------------------------------ \r
+;\r
+; CpuSleep() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+  EXPORT CpuSleep\r
+  AREA cpu_sleep, CODE, READONLY\r
+\r
+;/**\r
+;  Places the CPU in a sleep state until an interrupt is received.\r
+;\r
+;  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+;  are disabled prior to calling this function, then the CPU will be placed in a\r
+;  sleep state indefinitely.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;CpuSleep (\r
+;  VOID\r
+;  );\r
+;\r
+CpuSleep\r
+    MOV r0,#0\r
+    MCR p15,0,r0,c7,c0,4   ;Wait for Interrupt instruction\r
+    BX LR\r
+\r
+  END\r

diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 274722408369e3b811b584713ce080f2dfd01b10..567202a77937620dadc7262f84fb668a8a237029 100644 (file)
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -4,7 +4,8 @@
 #  CPU Library implemented using ASM functions for IA-32 and X64,\r
 #  PAL CALLs for IPF, and empty functions for EBC.\r
 #\r
-#  Copyright (c) 2007 - 2008, Intel Corporation.\r
+#  Copyright (c) 2007 - 2008, Intel Corporation.<BR>\r
+#  Portions Copyright (c) 2008-2009 Apple Inc.<BR>
 #\r
 #  All rights reserved. This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
@@ -26,12 +27,12 @@
 \r
 \r
 #\r
-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC ARM\r
 #\r
 \r
 [Sources.common]\r
 \r
-[Sources.Ia32]\r
+[Sources.IA32]\r
   Ia32/CpuSleep.c | MSFT \r
   Ia32/CpuFlushTlb.c | MSFT \r
 \r
@@ -55,10 +56,16 @@
 [Sources.EBC]\r
   Ebc/CpuSleepFlushTlb.c\r
 \r
+[Sources.ARM]
+  Arm/CpuFlushTlb.asm | RVCT
+  Arm/CpuSleep.asm    | RVCT  
+  Arm/CpuFlushTlb.S   | GCC
+  Arm/CpuSleep.S      | GCC  
+
 [Packages]\r
   MdePkg/MdePkg.dec\r
 \r
 \r
-[LibraryClasses.Ipf]\r
+[LibraryClasses.IPF]\r
   PalLib\r
   BaseLib
\ No newline at end of file

diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
new file mode 100644 (file)
index 0000000..1b27f79
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
@@ -0,0 +1,36 @@
+/** @file
+  CpuFlushTlb function for Ia32/X64 GCC.
+
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  Portions copyright (c) 2008-2009 Apple Inc.<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+/**
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+  VOID
+  )
+{
+  __asm__ __volatile__ (
+    "movl %%cr3, %0\n\t"
+    "movl %0, %%cr3    "
+    : "r"  // %0
+    );
+}
+

diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
new file mode 100644 (file)
index 0000000..a684059
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
@@ -0,0 +1,33 @@
+/** @file
+  CpuSleep function for Ia32/X64 GCC.
+
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  Portions copyright (c) 2008-2009 Apple Inc.<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+/**
+  Places the CPU in a sleep state until an interrupt is received.
+
+  Places the CPU in a sleep state until an interrupt is received. If interrupts
+  are disabled prior to calling this function, then the CPU will be placed in a
+  sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+  VOID
+  )
+{
+  __asm__ __volatile__ ("hlt"::: "memory");
+}
+