GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
\r
ASM_PFX(ArmPlatformPeiBootAction):\r
bx lr\r
movne r0, #0\r
bx lr\r
\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
+ // with cpu_id[0:3] and cluster_id[4:7]\r
+ LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0)\r
+ ldr r0, [r0]\r
+ lsr r0, #24\r
+\r
+ // Shift the SCC value to get the cluster ID at the offset #8\r
+ lsl r1, r0, #4\r
+ and r1, r1, #0xF00\r
+\r
+ // Keep only the cpu ID from the original SCC\r
+ and r0, r0, #0x0F\r
+ // Add the Cluster ID to the Cpu ID\r
+ orr r0, r0, r1\r
+ bx lr\r
EXPORT ArmPlatformPeiBootAction\r
EXPORT ArmPlatformGetCorePosition\r
EXPORT ArmPlatformIsPrimaryCore\r
+ EXPORT ArmPlatformGetPrimaryCoreMpId\r
\r
PRESERVE8\r
AREA CTA15A7Helper, CODE, READONLY\r
bx lr\r
ENDFUNC\r
\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ArmPlatformGetPrimaryCoreMpId FUNCTION\r
+ // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
+ // with cpu_id[0:3] and cluster_id[4:7]\r
+ LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0)\r
+ ldr r0, [r0]\r
+ lsr r0, #24\r
+\r
+ // Shift the SCC value to get the cluster ID at the offset #8\r
+ lsl r1, r0, #4\r
+ and r1, r1, #0xF00\r
+\r
+ // Keep only the cpu ID from the original SCC\r
+ and r0, r0, #0x0F\r
+ // Add the Cluster ID to the Cpu ID\r
+ orr r0, r0, r1\r
+ bx lr\r
+ ENDFUNC\r
+\r
END\r
\r
GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
\r
GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
// VOID\r
// );\r
ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
ldr r0, [r0]\r
bx lr\r
\r
// VOID\r
// );\r
ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
ldr r0, [r0]\r
bx lr\r
ENDFUNC\r
\r
GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
\r
ASM_PFX(ArmPlatformPeiBootAction):\r
ret\r
\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r
+ ldrh w0, [x0]\r
+ ret\r
+\r
# IN None\r
# OUT x0 = number of cores present in the system\r
ASM_PFX(ArmGetCpuCountPerCluster):\r
// VOID\r
// );\r
ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
ldr r0, [r0]\r
bx lr\r
\r
// VOID\r
// );\r
ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
ldr r0, [r0]\r
bx lr\r
ENDFUNC\r
// VOID\r
// );\r
ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
ldr r0, [r0]\r
bx lr\r
\r
// VOID\r
// );\r
ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r
ldr r0, [r0]\r
bx lr\r
ENDFUNC\r
.align 2\r
\r
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r
GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r
\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+\r
//UINTN\r
//ArmPlatformIsPrimaryCore (\r
// IN UINTN MpId\r
ASM_PFX(ArmPlatformPeiBootAction):\r
bx lr\r
\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r
+ // The BeagleBoard is a uniprocessor platform. The MPIDR of primary core is\r
+ // always the MPIDR of the calling CPU.\r
+ b ASM_PFX(ArmReadMpidr)\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
\r
EXPORT ArmPlatformPeiBootAction\r
EXPORT ArmPlatformIsPrimaryCore\r
+ EXPORT ArmPlatformGetPrimaryCoreMpId\r
+\r
+ IMPORT ArmReadMpidr\r
\r
AREA BeagleBoardHelper, CODE, READONLY\r
\r
bx lr\r
ENDFUNC\r
\r
+//UINTN\r
+//ArmPlatformGetPrimaryCoreMpId (\r
+// VOID\r
+// );\r
+ArmPlatformGetPrimaryCoreMpId FUNCTION\r
+ // The BeagleBoard is a uniprocessor platform. The MPIDR of primary core is\r
+ // always the MPIDR of the calling CPU.\r
+ b ArmReadMpidr\r
+ ENDFUNC\r
+\r
END\r