UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob

UefiPayload parse gUniversalPayloadPciRootBridgeInfoGuid Guid Hob to
retrieve PCI root bridges information.
gUniversalPayloadPciRootBridgeInfoGuid Guid Hob should be created by
Bootloader.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
index c2961b3bee1b6aaa2f36656d530a9cbe6434c286..3eee1fbeac863f2e41b1a463fc1aeeaa5d15c63c 100644 (file)
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
@@ -2,7 +2,7 @@
   Header file of PciHostBridgeLib.\r
 \r
   Copyright (C) 2016, Red Hat, Inc.\r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -11,14 +11,38 @@
 #ifndef _PCI_HOST_BRIDGE_H\r
 #define _PCI_HOST_BRIDGE_H\r
 \r
+#include <UniversalPayload/PciRootBridges.h>\r
+\r
 typedef struct {\r
   ACPI_HID_DEVICE_PATH     AcpiDevicePath;\r
   EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
 } CB_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
 \r
+/**\r
+  Scan for all root bridges in platform.\r
+\r
+  @param[out] NumberOfRootBridges  Number of root bridges detected\r
+\r
+  @retval     Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
+**/\r
 PCI_ROOT_BRIDGE *\r
 ScanForRootBridges (\r
-  UINTN      *NumberOfRootBridges\r
+  OUT UINTN      *NumberOfRootBridges\r
+);\r
+\r
+/**\r
+  Scan for all root bridges from Universal Payload PciRootBridgeInfoHob\r
+\r
+  @param[in]  PciRootBridgeInfo    Pointer of Universal Payload PCI Root Bridge Info Hob\r
+  @param[out] NumberOfRootBridges  Number of root bridges detected\r
+\r
+  @retval     Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
+\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+RetrieveRootBridgeInfoFromHob (\r
+  IN  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES  *PciRootBridgeInfo,\r
+  OUT UINTN                               *NumberOfRootBridges\r
 );\r
 \r
 /**\r
@@ -77,4 +101,16 @@ InitRootBridge (
   OUT PCI_ROOT_BRIDGE          *RootBus\r
 );\r
 \r
+/**\r
+  Initialize DevicePath for a PCI_ROOT_BRIDGE.\r
+  @param[in] HID               HID for device path\r
+  @param[in] UID               UID for device path\r
+\r
+  @retval A pointer to the new created device patch.\r
+**/\r
+EFI_DEVICE_PATH_PROTOCOL *\r
+CreateRootBridgeDevicePath (\r
+  IN     UINT32                   HID,\r
+  IN     UINT32                   UID\r
+);\r
 #endif\r

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 512c3127cc5631d8761a4b5e9fec2e79515af24a..a0d7cdc306fc13f5510443668af7a0112166a3c9 100644 (file)
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -2,7 +2,7 @@
   Library instance of PciHostBridgeLib library class for coreboot.\r
 \r
   Copyright (C) 2016, Red Hat, Inc.\r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -19,6 +19,7 @@
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/PciHostBridgeLib.h>\r
 #include <Library/PciLib.h>\r
+#include <Library/HobLib.h>\r
 \r
 #include "PciHostBridge.h"\r
 \r
@@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
   }\r
 };\r
 \r
-\r
 /**\r
   Initialize a PCI_ROOT_BRIDGE structure.\r
 \r
@@ -145,6 +145,27 @@ InitRootBridge (
   return EFI_SUCCESS;\r
 }\r
 \r
+/**\r
+  Initialize DevicePath for a PCI_ROOT_BRIDGE.\r
+  @param[in] HID               HID for device path\r
+  @param[in] UID               UID for device path\r
+\r
+  @retval A pointer to the new created device patch.\r
+**/\r
+EFI_DEVICE_PATH_PROTOCOL *\r
+CreateRootBridgeDevicePath (\r
+  IN     UINT32                   HID,\r
+  IN     UINT32                   UID\r
+)\r
+{\r
+  CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
+  DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),\r
+                                 &mRootBridgeDevicePathTemplate);\r
+  ASSERT (DevicePath != NULL);\r
+  DevicePath->AcpiDevicePath.HID = HID;\r
+  DevicePath->AcpiDevicePath.UID = UID;\r
+  return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
+}\r
 \r
 /**\r
   Return all the root bridge instances in an array.\r
@@ -161,10 +182,30 @@ PciHostBridgeGetRootBridges (
   UINTN *Count\r
 )\r
 {\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES  *PciRootBridgeInfo;\r
+  EFI_HOB_GUID_TYPE                   *GuidHob;\r
+  UNIVERSAL_PAYLOAD_GENERIC_HEADER    *GenericHeader;\r
+  //\r
+  // Find Universal Payload PCI Root Bridge Info hob\r
+  //\r
+  GuidHob = GetFirstGuidHob (&gUniversalPayloadPciRootBridgeInfoGuid);\r
+  if (GuidHob != NULL) {\r
+    GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *) GET_GUID_HOB_DATA (GuidHob);\r
+    if ((sizeof(UNIVERSAL_PAYLOAD_GENERIC_HEADER) <= GET_GUID_HOB_DATA_SIZE (GuidHob)) && (GenericHeader->Length <= GET_GUID_HOB_DATA_SIZE (GuidHob))) {\r
+      if ((GenericHeader->Revision == UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION) && (GenericHeader->Length >= sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES))) {\r
+        //\r
+        // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES structure is used when Revision equals to UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION\r
+        //\r
+        PciRootBridgeInfo = (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *) GET_GUID_HOB_DATA (GuidHob);\r
+        if (PciRootBridgeInfo->Count <= (GET_GUID_HOB_DATA_SIZE (GuidHob) - sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES)) / sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE)) {\r
+          return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);\r
+        }\r
+      }\r
+    }\r
+  }\r
   return ScanForRootBridges (Count);\r
 }\r
 \r
-\r
 /**\r
   Free the root bridge instances array returned from\r
   PciHostBridgeGetRootBridges().\r

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 7896df2416c97300842a1cd027583abb3eab376c..6069dcc0efa3f67a729c3e27380d62f2f7ddd9f1 100644 (file)
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -2,7 +2,7 @@
 #  Library instance of PciHostBridgeLib library class for coreboot.\r
 #\r
 #  Copyright (C) 2016, Red Hat, Inc.\r
-#  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
 #\r
 #  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -39,3 +39,9 @@
   DevicePathLib\r
   MemoryAllocationLib\r
   PciLib\r
+\r
+[Guids]\r
+  gUniversalPayloadPciRootBridgeInfoGuid\r
+\r
+[Pcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index fffbf04cad3fc746e1b9e2d9e1ad7cef23ad3a81..b0268f05069ce6b0bf3d39cccf185d6f00f2a739 100644 (file)
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -582,3 +582,74 @@ ScanForRootBridges (
 \r
   return RootBridges;\r
 }\r
+\r
+/**\r
+  Scan for all root bridges from Universal Payload PciRootBridgeInfoHob\r
+\r
+  @param[in]  PciRootBridgeInfo    Pointer of Universal Payload PCI Root Bridge Info Hob\r
+  @param[out] NumberOfRootBridges  Number of root bridges detected\r
+\r
+  @retval     Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
+\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+RetrieveRootBridgeInfoFromHob (\r
+  IN  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES  *PciRootBridgeInfo,\r
+  OUT UINTN                               *NumberOfRootBridges\r
+)\r
+{\r
+  PCI_ROOT_BRIDGE                *PciRootBridges;\r
+  UINTN                          Size;\r
+  UINT8                          Index;\r
+\r
+  ASSERT (PciRootBridgeInfo != NULL);\r
+  ASSERT (NumberOfRootBridges != NULL);\r
+  if (PciRootBridgeInfo == NULL) {\r
+    return NULL;\r
+  }\r
+  if (PciRootBridgeInfo->Count == 0) {\r
+    return NULL;\r
+  }\r
+  Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);\r
+  PciRootBridges = (PCI_ROOT_BRIDGE *) AllocatePool (Size);\r
+  ASSERT (PciRootBridges != NULL);\r
+  if (PciRootBridges == NULL) {\r
+    return NULL;\r
+  }\r
+  ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE));\r
+\r
+  //\r
+  // Create all root bridges with PciRootBridgeInfoHob\r
+  //\r
+  for (Index = 0; Index < PciRootBridgeInfo->Count; Index++) {\r
+    PciRootBridges[Index].Segment               = PciRootBridgeInfo->RootBridge[Index].Segment;\r
+    PciRootBridges[Index].Supports              = PciRootBridgeInfo->RootBridge[Index].Supports;\r
+    PciRootBridges[Index].Attributes            = PciRootBridgeInfo->RootBridge[Index].Attributes;\r
+    PciRootBridges[Index].DmaAbove4G            = PciRootBridgeInfo->RootBridge[Index].DmaAbove4G;\r
+    PciRootBridges[Index].NoExtendedConfigSpace = PciRootBridgeInfo->RootBridge[Index].NoExtendedConfigSpace;\r
+    PciRootBridges[Index].ResourceAssigned      = PciRootBridgeInfo->ResourceAssigned;\r
+    PciRootBridges[Index].AllocationAttributes  = PciRootBridgeInfo->RootBridge[Index].AllocationAttributes;\r
+    PciRootBridges[Index].DevicePath            = CreateRootBridgeDevicePath(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridge[Index].UID);\r
+    CopyMem(&PciRootBridges[Index].Bus,         &PciRootBridgeInfo->RootBridge[Index].Bus,         sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].Io,          &PciRootBridgeInfo->RootBridge[Index].Io,          sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].Mem,         &PciRootBridgeInfo->RootBridge[Index].Mem,         sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].MemAbove4G,  &PciRootBridgeInfo->RootBridge[Index].MemAbove4G,  sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].PMem,        &PciRootBridgeInfo->RootBridge[Index].PMem,        sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBridge[Index].PMemAbove4G, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+  }\r
+\r
+  *NumberOfRootBridges = PciRootBridgeInfo->Count;\r
+\r
+  //\r
+  // Now, this library only supports RootBridge that ResourceAssigned is True\r
+  //\r
+  if (PciRootBridgeInfo->ResourceAssigned) {\r
+    PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);\r
+  } else {\r
+    DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is FALSE\n"));\r
+    PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);\r
+    return NULL;\r
+  }\r
+\r
+  return PciRootBridges;\r
+}\r

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 37ad5a0ae71b73b72a51b5a731d0475d37e77478..e9211adf86e582807773dca436384836e4955951 100644 (file)
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -323,7 +323,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)\r
 \r
-  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)\r
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)\r
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)\r
@@ -363,6 +362,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100\r
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0\r
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
 \r
 ################################################################################\r
 #\r