MdePkg/BaseLib: Add support for the XGETBV instruction

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

Under SEV-ES, a CPUID instruction requires the current value of the XCR0
register. In order to retrieve that value, the XGETBV instruction needs
to be executed.

Provide the necessary support to execute the XGETBV instruction.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 8e7b87cbda4e500ecbf56d1c5d59a69899a2c792..7edf0051a0a0c2360964bcf7f5e7216c75656772 100644 (file)
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -7831,6 +7831,23 @@ AsmLfence (
   VOID\r
   );\r
 \r
+/**\r
+  Executes a XGETBV instruction\r
+\r
+  Executes a XGETBV instruction. This function is only available on IA-32 and\r
+  x64.\r
+\r
+  @param[in] Index        Extended control register index\r
+\r
+  @return                 The current value of the extended control register\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmXGetBv (\r
+  IN UINT32  Index\r
+  );\r
+\r
+\r
 /**\r
   Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
   word, dword or qword operand is encoded at the end of the instruction's\r

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index c740a819cacf52d62a7c424fcb417c39334a620e..3b93b5db8d24f0e576284cb1978c41393a864da5 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -183,6 +183,7 @@
   Ia32/EnableCache.nasm| GCC\r
   Ia32/DisableCache.nasm| GCC\r
   Ia32/RdRand.nasm\r
+  Ia32/XGetBv.nasm\r
 \r
   Ia32/DivS64x64Remainder.c\r
   Ia32/InternalSwitchStack.c | MSFT\r
@@ -315,6 +316,7 @@
   X64/EnableDisableInterrupts.nasm\r
   X64/DisablePaging64.nasm\r
   X64/RdRand.nasm\r
+  X64/XGetBv.nasm\r
   ChkStkGcc.c  | GCC\r
 \r
 [Sources.EBC]\r

diff --git a/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
new file mode 100644 (file)
index 0000000..9f7b03b
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
@@ -0,0 +1,31 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Module Name:\r
+;\r
+;   XGetBv.Asm\r
+;\r
+; Abstract:\r
+;\r
+;   AsmXgetBv function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmXGetBv (\r
+;   IN UINT32  Index\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmXGetBv)\r
+ASM_PFX(AsmXGetBv):\r
+    mov     ecx, [esp + 4]\r
+    xgetbv\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/MdePkg/Library/BaseLib/X64/XGetBv.nasm
new file mode 100644 (file)
index 0000000..09f3be8
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/XGetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Module Name:\r
+;\r
+;   XGetBv.Asm\r
+;\r
+; Abstract:\r
+;\r
+;   AsmXgetBv function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    DEFAULT REL\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmXGetBv (\r
+;   IN UINT32  Index\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmXGetBv)\r
+ASM_PFX(AsmXGetBv):\r
+    xgetbv\r
+    shl     rdx, 32\r
+    or      rax, rdx\r
+    ret\r
+\r