BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
\r
NorFlashPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/NorFlashArmRealViewEbLib/NorFlashArmRealViewEbLib.inf\r
+ LcdPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/PL111LcdArmRealViewEbLib/PL111LcdArmRealViewEbLib.inf\r
\r
[LibraryClasses.common.SEC]\r
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
\r
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf\r
+ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
\r
ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf\r
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
NorFlashPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/NorFlashArmRealViewEbLib/NorFlashArmRealViewEbLib.inf
+ LcdPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/PL111LcdArmRealViewEbLib/PL111LcdArmRealViewEbLib.inf
[LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
+\r
+ INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
\r
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf\r
\r
*******************************************/\r
\r
// Can be NOR, DOC, DRAM, SRAM\r
-#define ARM_EB_REMAP_BASE 0x00000000\r
-#define ARM_EB_REMAP_SZ 0x04000000\r
+#define ARM_EB_REMAP_BASE 0x00000000\r
+#define ARM_EB_REMAP_SZ 0x04000000\r
\r
// Motherboard Peripheral and On-chip peripheral\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000\r
-#define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r
-//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
+#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000\r
+#define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r
+//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r
\r
// SMC\r
-#define ARM_EB_SMC_BASE 0x40000000\r
-#define ARM_EB_SMC_SZ 0x20000000\r
+#define ARM_EB_SMC_BASE 0x40000000\r
+#define ARM_EB_SMC_SZ 0x20000000\r
\r
// NOR Flash 1\r
-#define ARM_EB_SMB_NOR_BASE 0x40000000\r
-#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r
+#define ARM_EB_SMB_NOR_BASE 0x40000000\r
+#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r
// DOC Flash\r
-#define ARM_EB_SMB_DOC_BASE 0x44000000\r
-#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r
+#define ARM_EB_SMB_DOC_BASE 0x44000000\r
+#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r
// SRAM\r
-#define ARM_EB_SMB_SRAM_BASE 0x48000000\r
-#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
+#define ARM_EB_SMB_SRAM_BASE 0x48000000\r
+#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
// USB, Ethernet, VRAM\r
-#define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r
-//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r
-#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r
+#define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r
+//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r
+#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r
\r
// DRAM\r
-#define ARM_EB_DRAM_BASE 0x70000000\r
-#define ARM_EB_DRAM_SZ 0x10000000\r
+#define ARM_EB_DRAM_BASE 0x70000000\r
+#define ARM_EB_DRAM_SZ 0x10000000\r
\r
// Logic Tile\r
-#define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r
-#define ARM_EB_LOGIC_TILE_SZ 0x40000000\r
+#define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r
+#define ARM_EB_LOGIC_TILE_SZ 0x40000000\r
\r
/*******************************************\r
// Motherboard peripherals\r
*******************************************/\r
\r
// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
-#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
-#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
-#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
-#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
-#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
-#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
-#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
+#define ARM_EB_SYS_OSC4_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)\r
+#define ARM_EB_SYS_LOCK_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00020)\r
+#define ARM_EB_SYS_100HZ_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00024)\r
+#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_EB_SYS_CLCD_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
+#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
\r
// SP810 Controller\r
-#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
+#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
\r
// SYSTRCL Register\r
-#define ARM_EB_SYSCTRL 0x10001000\r
+#define ARM_EB_SYSCTRL 0x10001000\r
\r
// Uart0\r
-#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
-#define PL011_CONSOLE_UART_SPEED 115200\r
+#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
\r
// SP804 Timer Bases\r
-#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
-#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
-#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
-#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
+#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
\r
// Dynamic Memory Controller Base\r
#define ARM_EB_DMC_BASE 0x10018000\r
\r
// Static Memory Controller Base\r
#define ARM_EB_SMC_CTRL_BASE 0x10080000\r
+#define PL111_CLCD_BASE 0x10020000\r
+//Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work\r
+#define PL111_CLCD_VRAM_BASE 0x00100000\r
\r
/*// System Configuration Controller register Base addresses\r
//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/LcdPlatformLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Drivers/PL111Lcd.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+typedef struct {\r
+ UINT32 Mode;\r
+ UINT32 HorizontalResolution;\r
+ UINT32 VerticalResolution;\r
+ LCD_BPP Bpp;\r
+ UINT32 ClcdClk;\r
+\r
+ UINT32 HSync;\r
+ UINT32 HBackPorch;\r
+ UINT32 HFrontPorch;\r
+ UINT32 VSync;\r
+ UINT32 VBackPorch;\r
+ UINT32 VFrontPorch;\r
+} CLCD_RESOLUTION;\r
+\r
+\r
+CLCD_RESOLUTION mResolutions[] = {\r
+ { // Mode 0 : VGA : 640 x 480 x 24 bpp\r
+ VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, 0x2C77,\r
+ VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
+ VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
+ },\r
+ { // Mode 1 : SVGA : 800 x 600 x 24 bpp\r
+ SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, 0x2CAC,\r
+ SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
+ SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
+ }\r
+};\r
+\r
+\r
+EFI_STATUS\r
+LcdPlatformInitializeDisplay (\r
+ VOID\r
+ )\r
+{\r
+ MmioWrite32(ARM_EB_SYS_CLCD_REG, 1);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformGetVram (\r
+ OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
+ OUT UINTN* VramSize\r
+ )\r
+{\r
+ *VramBaseAddress = PL111_CLCD_VRAM_BASE;\r
+ *VramSize = SIZE_8MB; //FIXME: Can this size change ?\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+UINT32\r
+LcdPlatformGetMaxMode (\r
+ VOID\r
+ )\r
+{\r
+ return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION));\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformSetMode (\r
+ IN UINT32 ModeNumber\r
+ )\r
+{\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ MmioWrite32(ARM_EB_SYS_LOCK_REG,0x0000A05F);\r
+ MmioWrite32(ARM_EB_SYS_OSC4_REG,mResolutions[ModeNumber].ClcdClk);\r
+ MmioWrite32(ARM_EB_SYS_LOCK_REG,0x0);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformQueryMode (\r
+ IN UINT32 ModeNumber,\r
+ OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = EFI_UNSUPPORTED;\r
+\r
+ Info->Version = 0;\r
+ Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r
+ Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r
+ Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r
+\r
+ switch (mResolutions[ModeNumber].Bpp) {\r
+ case LCD_BITS_PER_PIXEL_24:\r
+ Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r
+ Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;\r
+ Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;\r
+ Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;\r
+ Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r
+ Status = EFI_SUCCESS;\r
+ break;\r
+\r
+ case LCD_BITS_PER_PIXEL_16_555:\r
+ Info->PixelFormat = PixelBitMask;\r
+ Info->PixelInformation.RedMask = LCD_16BPP_555_RED_MASK;\r
+ Info->PixelInformation.GreenMask = LCD_16BPP_555_GREEN_MASK;\r
+ Info->PixelInformation.BlueMask = LCD_16BPP_555_BLUE_MASK;\r
+ Info->PixelInformation.ReservedMask = LCD_16BPP_555_RESERVED_MASK;\r
+ Status = EFI_SUCCESS;\r
+ break;\r
+\r
+ case LCD_BITS_PER_PIXEL_16_565:\r
+ Info->PixelFormat = PixelBitMask;\r
+ Info->PixelInformation.RedMask = LCD_16BPP_565_RED_MASK;\r
+ Info->PixelInformation.GreenMask = LCD_16BPP_565_GREEN_MASK;\r
+ Info->PixelInformation.BlueMask = LCD_16BPP_565_BLUE_MASK;\r
+ Info->PixelInformation.ReservedMask = LCD_16BPP_565_RESERVED_MASK;\r
+ Status = EFI_SUCCESS;\r
+ break;\r
+\r
+ case LCD_BITS_PER_PIXEL_12_444:\r
+ Info->PixelFormat = PixelBitMask;\r
+ Info->PixelInformation.RedMask = LCD_12BPP_444_RED_MASK;\r
+ Info->PixelInformation.GreenMask = LCD_12BPP_444_GREEN_MASK;\r
+ Info->PixelInformation.BlueMask = LCD_12BPP_444_BLUE_MASK;\r
+ Info->PixelInformation.ReservedMask = LCD_12BPP_444_RESERVED_MASK;\r
+ Status = EFI_SUCCESS;\r
+ break;\r
+\r
+ case LCD_BITS_PER_PIXEL_8:\r
+ case LCD_BITS_PER_PIXEL_4:\r
+ case LCD_BITS_PER_PIXEL_2:\r
+ case LCD_BITS_PER_PIXEL_1:\r
+ default:\r
+ // These are not supported\r
+ break;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformGetTimings (\r
+ IN UINT32 ModeNumber,\r
+ OUT UINT32* HRes,\r
+ OUT UINT32* HSync,\r
+ OUT UINT32* HBackPorch,\r
+ OUT UINT32* HFrontPorch,\r
+ OUT UINT32* VRes,\r
+ OUT UINT32* VSync,\r
+ OUT UINT32* VBackPorch,\r
+ OUT UINT32* VFrontPorch\r
+ )\r
+{\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *HRes = mResolutions[ModeNumber].HorizontalResolution;\r
+ *HSync = mResolutions[ModeNumber].HSync;\r
+ *HBackPorch = mResolutions[ModeNumber].HBackPorch;\r
+ *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;\r
+ *VRes = mResolutions[ModeNumber].VerticalResolution;\r
+ *VSync = mResolutions[ModeNumber].VSync;\r
+ *VBackPorch = mResolutions[ModeNumber].VBackPorch;\r
+ *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+LcdPlatformGetBpp (\r
+ IN UINT32 ModeNumber,\r
+ OUT LCD_BPP * Bpp\r
+ )\r
+{\r
+ if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *Bpp = mResolutions[ModeNumber].Bpp;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+#/** @file
+#
+# Component discription file for ArmVeGraphicsDxe module
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL111LcdArmRealViewEbLib
+ FILE_GUID = 51396ee0-4973-11e0-868a-0002a5d5c51b
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PL111LcdPlatformLib
+
+[Sources.common]
+ PL111LcdArmRealViewEb.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+
+[Guids]
+
+[Protocols]
+
+[FixedPcd.common]
+
+ #
+ # The following modes are supported by PL111
+ #
+ # 0 : 640 x 480 x 24 bpp
+ # 1 : 800 x 600 x 24 bpp
+ # 2 : 1024 x 768 x 24 bpp
+ # 3 : 640 x 480 x 16 bpp (565 RGB Mode)
+ # 4 : 800 x 600 x 16 bpp (565 RGB Mode)
+ # 5 : 1024 x 768 x 16 bpp (565 RGB Mode)
+ # 6 : 640 x 480 x 15 bpp (555 RGB Mode)
+ # 7 : 800 x 600 x 15 bpp (555 RGB Mode)
+ # 8 : 1024 x 768 x 15 bpp (555 RGB Mode)
+ # 9 : 1024 x 768 x 15 bpp (555 RGB Mode) - Linux driver settings
+ # 10 : 640 x 480 x 12 bpp (444 RGB Mode)
+ # 11 : 800 x 600 x 12 bpp (444 RGB Mode)
+ # 12 : 1024 x 768 x 12 bpp (444 RGB Mode)
+ #
+
+[Pcd.common]
+
+[Depex]
+ # gEfiCpuArchProtocolGuid