/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
- // Give control back to bootloader after FspInit\r
+ // Give control back to BootLoader after FspInit\r
//\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP is waiting for NOTIFY\n"));\r
FspInitDone ();\r
\r
//\r
- // Bootloader called FSP again through NotifyPhase\r
+ // BootLoader called FSP again through NotifyPhase\r
//\r
FspWaitForNotify ();\r
\r
Ia32/Stack.asm | MSFT\r
Ia32/InitializeFpu.asm | MSFT\r
Ia32/FspApiEntry.asm | MSFT\r
+ Ia32/FspHelper.asm | MSFT\r
\r
Ia32/Stacks.s | GCC\r
Ia32/InitializeFpu.s | GCC\r
Ia32/FspApiEntry.s | GCC\r
+ Ia32/FspHelper.s | GCC\r
\r
[Binaries.Ia32]\r
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r
SerialPortLib\r
FspSwitchStackLib\r
FspCommonLib\r
+ FspSecPlatformLib\r
\r
[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED\r
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES\r
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES\r
gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase ## CONSUMES\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress ## CONSUMES\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize ## CONSUMES\r
\r
[FixedPcd]\r
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES\r
.xmm\r
\r
INCLUDE SaveRestoreSse.inc\r
-INCLUDE UcodeLoad.inc\r
+INCLUDE MicrocodeLoad.inc\r
\r
;\r
; Following are fixed PCDs\r
EXTERN GetFspBaseAddress:PROC\r
EXTERN GetBootFirmwareVolumeOffset:PROC\r
EXTERN Pei2LoaderSwitchStack:PROC\r
-EXTERN FspSelfCheck(FspSelfCheckDefault):PROC\r
-EXTERN LoadUcode(LoadUcodeDefault):PROC\r
+EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC\r
EXTERN SecPlatformInit(SecPlatformInitDefault):PROC\r
EXTERN SecCarInit:PROC\r
\r
ENDM\r
\r
RET_ESI_EXT MACRO MmxRegister\r
- movd esi, MmxRegister ; restore ESP from MMX\r
+ movd esi, MmxRegister ; move ReturnAddress from MMX to ESI\r
jmp esi\r
ENDM\r
\r
ENDM\r
\r
RET_ESI MACRO\r
- RET_ESI_EXT mm7 \r
+ RET_ESI_EXT mm7\r
ENDM\r
\r
-;------------------------------------------------------------------------------\r
-FspSelfCheckDefault PROC NEAR PUBLIC\r
- ; Inputs:\r
- ; eax -> Return address\r
- ; Outputs:\r
- ; eax -> 0 - Successful, Non-zero - Failed.\r
- ; Register Usage:\r
- ; eax is cleared and ebp is used for return address.\r
- ; All others reserved.\r
-\r
- ; Save return address to EBP\r
- mov ebp, eax\r
-\r
- xor eax, eax\r
-exit:\r
- jmp ebp\r
-FspSelfCheckDefault ENDP\r
-\r
;------------------------------------------------------------------------------\r
SecPlatformInitDefault PROC NEAR PUBLIC\r
; Inputs:\r
SecPlatformInitDefault ENDP\r
\r
;------------------------------------------------------------------------------\r
-LoadUcodeDefault PROC NEAR PUBLIC\r
+LoadMicrocodeDefault PROC NEAR PUBLIC\r
; Inputs:\r
- ; esp -> LOAD_UCODE_PARAMS pointer\r
+ ; esp -> LoadMicrocodeParams pointer\r
; Register Usage:\r
; esp Preserved\r
; All others destroyed\r
\r
cmp esp, 0\r
jz paramerror\r
- mov eax, dword ptr [esp] ; Parameter pointer\r
+ mov eax, dword ptr [esp + 4] ; Parameter pointer\r
cmp eax, 0\r
jz paramerror\r
mov esp, eax\r
- mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
cmp esi, 0\r
jnz check_main_header\r
\r
mov eax, 080000002h\r
jmp exit\r
\r
- mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
\r
check_main_header:\r
; Get processor signature and platform ID from the installed processor\r
; Check for valid microcode header\r
; Minimal test checking for header version and loader version as 1\r
mov eax, dword ptr 1\r
- cmp [esi].ucode_hdr.version, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrVersion, eax\r
jne advance_fixed_size\r
- cmp [esi].ucode_hdr.loader, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrLoader, eax\r
jne advance_fixed_size\r
\r
; Check if signature and plaform ID match\r
- cmp ebx, [esi].ucode_hdr.processor\r
+ cmp ebx, [esi].MicrocodeHdr.MicrocodeHdrProcessor\r
jne @f\r
- test edx, [esi].ucode_hdr.flags\r
+ test edx, [esi].MicrocodeHdr.MicrocodeHdrFlags\r
jnz load_check ; Jif signature and platform ID match\r
\r
@@:\r
; Check if extended header exists\r
- ; First check if total_size and data_size are valid\r
+ ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
xor eax, eax\r
- cmp [esi].ucode_hdr.total_size, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax\r
je next_microcode\r
- cmp [esi].ucode_hdr.data_size, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrDataSize, eax\r
je next_microcode\r
\r
; Then verify total size - sizeof header > data size\r
- mov ecx, [esi].ucode_hdr.total_size\r
- sub ecx, sizeof ucode_hdr\r
- cmp ecx, [esi].ucode_hdr.data_size\r
+ mov ecx, [esi].MicrocodeHdr.MicrocodeHdrTotalSize\r
+ sub ecx, sizeof MicrocodeHdr\r
+ cmp ecx, [esi].MicrocodeHdr.MicrocodeHdrDataSize\r
jng next_microcode ; Jif extended header does not exist\r
\r
; Set edi -> extended header\r
mov edi, esi\r
- add edi, sizeof ucode_hdr\r
- add edi, [esi].ucode_hdr.data_size\r
+ add edi, sizeof MicrocodeHdr\r
+ add edi, [esi].MicrocodeHdr.MicrocodeHdrDataSize\r
\r
; Get count of extended structures\r
- mov ecx, [edi].ext_sig_hdr.count\r
+ mov ecx, [edi].ExtSigHdr.ExtSigHdrCount\r
\r
; Move pointer to first signature structure\r
- add edi, sizeof ext_sig_hdr\r
+ add edi, sizeof ExtSigHdr\r
\r
check_ext_sig:\r
; Check if extended signature and platform ID match\r
- cmp [edi].ext_sig.processor, ebx\r
+ cmp [edi].ExtSig.ExtSigProcessor, ebx\r
jne @f\r
- test [edi].ext_sig.flags, edx\r
+ test [edi].ExtSig.ExtSigFlags, edx\r
jnz load_check ; Jif signature and platform ID match\r
@@:\r
; Check if any more extended signatures exist\r
- add edi, sizeof ext_sig\r
+ add edi, sizeof ExtSig\r
loop check_ext_sig\r
\r
next_microcode:\r
; Advance just after end of this microcode\r
xor eax, eax\r
- cmp [esi].ucode_hdr.total_size, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax\r
je @f\r
- add esi, [esi].ucode_hdr.total_size\r
+ add esi, [esi].MicrocodeHdr.MicrocodeHdrTotalSize\r
jmp check_address\r
@@:\r
add esi, dword ptr 2048\r
\r
check_address:\r
; Is valid Microcode start point ?\r
- cmp dword ptr [esi].ucode_hdr.version, 0ffffffffh\r
+ cmp dword ptr [esi].MicrocodeHdr.MicrocodeHdrVersion, 0ffffffffh\r
jz done\r
\r
; Is automatic size detection ?\r
- mov eax, [esp].LOAD_UCODE_PARAMS.ucode_code_size\r
+ mov eax, [esp].LoadMicrocodeParams.MicrocodeCodeSize\r
cmp eax, 0ffffffffh\r
jz @f\r
\r
; Address >= microcode region address + microcode region size?\r
- add eax, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ add eax, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
cmp esi, eax\r
- jae done ;Jif address is outside of ucode region\r
+ jae done ;Jif address is outside of microcode region\r
jmp check_main_header\r
\r
@@:\r
rdmsr ; Get current microcode signature\r
\r
; Verify this microcode update is not already loaded\r
- cmp [esi].ucode_hdr.revision, edx\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrRevision, edx\r
je continue\r
\r
load_microcode:\r
; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r
; Start microcode load with wrmsr\r
mov eax, esi\r
- add eax, sizeof ucode_hdr\r
+ add eax, sizeof MicrocodeHdr\r
xor edx, edx\r
mov ecx, MSR_IA32_BIOS_UPDT_TRIG\r
wrmsr\r
exit:\r
jmp ebp\r
\r
-LoadUcodeDefault ENDP\r
+LoadMicrocodeDefault ENDP\r
\r
EstablishStackFsp PROC NEAR PRIVATE\r
;\r
- ; Save parameter pointer in edx \r
+ ; Save parameter pointer in edx\r
;\r
- mov edx, dword ptr [esp + 4] \r
- \r
+ mov edx, dword ptr [esp + 4]\r
+\r
;\r
; Enable FSP STACK\r
;\r
mov esp, PcdGet32 (PcdTemporaryRamBase)\r
- add esp, PcdGet32 (PcdTemporaryRamSize) \r
+ add esp, PcdGet32 (PcdTemporaryRamSize)\r
\r
- push DATA_LEN_OF_MCUD ; Size of the data region \r
+ push DATA_LEN_OF_MCUD ; Size of the data region\r
push 4455434Dh ; Signature of the data region 'MCUD'\r
push dword ptr [edx + 12] ; Code size\r
push dword ptr [edx + 8] ; Code base\r
- cmp edx, 0 ; Is parameter pointer valid ?\r
- jz InvalidMicrocodeRegion\r
push dword ptr [edx + 4] ; Microcode size\r
- push dword ptr [edx] ; Microcode base \r
- jmp @F\r
+ push dword ptr [edx] ; Microcode base\r
\r
-InvalidMicrocodeRegion:\r
- push 0 ; Microcode size\r
- push 0 ; Microcode base\r
- \r
-@@:\r
;\r
; Save API entry/exit timestamp into stack\r
;\r
push 0\r
\r
;\r
- ; Set ECX/EDX to the bootloader temporary memory range\r
+ ; Set ECX/EDX to the BootLoader temporary memory range\r
;\r
mov ecx, PcdGet32 (PcdTemporaryRamBase)\r
mov edx, ecx\r
sub edx, PcdGet32 (PcdFspTemporaryRamSize)\r
\r
xor eax, eax\r
- \r
+\r
RET_ESI\r
\r
EstablishStackFsp ENDP\r
\r
;\r
; CPUID/DeviceID check\r
+ ; and Sec Platform Init\r
;\r
- mov eax, @F\r
- jmp FspSelfCheck ; Note: ESP can not be changed.\r
-@@:\r
- cmp eax, 0\r
- jnz NemInitExit\r
-\r
CALL_MMX SecPlatformInit\r
cmp eax, 0\r
jnz NemInitExit\r
\r
; Load microcode\r
LOAD_ESP\r
- CALL_MMX LoadUcode\r
- cmp eax, 0\r
- jnz NemInitExit\r
+ CALL_MMX LoadMicrocode\r
+ SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.\r
+ ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
\r
; Call Sec CAR Init\r
LOAD_ESP\r
LOAD_ESP\r
CALL_MMX EstablishStackFsp\r
\r
+ LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
+\r
NemInitExit:\r
;\r
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
; Verify the calling condition\r
;\r
pushad\r
+ push [esp + 4 * 8 + 4]\r
push eax\r
call FspApiCallingCheck\r
- add esp, 4\r
+ add esp, 8\r
cmp eax, 0\r
jz @F\r
mov dword ptr [esp + 4 * 7], eax\r
jz @F\r
jmp Pei2LoaderSwitchStack\r
\r
-@@: \r
+@@:\r
;\r
; FspInit and FspMemoryInit APIs, setup the initial stack frame\r
- ; \r
+ ;\r
\r
;\r
; Store the address in FSP which will return control to the BL\r
\r
; Reserve 8 bytes for IDT save/restore\r
sub esp, 8\r
- sidt fword ptr [esp] \r
+ sidt fword ptr [esp]\r
\r
;\r
; Setup new FSP stack\r
push eax\r
\r
;\r
- ; Pass the bootloader stack to SecStartup\r
+ ; Pass the BootLoader stack to SecStartup\r
;\r
push edi\r
\r
;\r
call SecStartup\r
\r
-exit: \r
+exit:\r
ret\r
\r
FspApiCommon ENDP\r
#\r
#------------------------------------------------------------------------------\r
\r
-#.INCLUDE "UcodeLoadGcc.inc" - begin\r
\r
.equ MSR_IA32_PLATFORM_ID, 0x00000017\r
.equ MSR_IA32_BIOS_UPDT_TRIG, 0x00000079\r
.equ MSR_IA32_BIOS_SIGN_ID, 0x0000008b\r
\r
-Ucode:\r
-.equ UcodeVersion, 0x0000\r
-.equ UcodeRevision, 0x0004\r
-.equ UcodeDate, 0x0008\r
-.equ UcodeProcessor, 0x000C\r
-.equ UcodeChecksum, 0x0010\r
-.equ UcodeLoader, 0x0014\r
-.equ UcodeRsvd, 0x0018\r
-UcodeEnd:\r
-\r
-UcodeHdr:\r
-.equ UcodeHdrVersion, 0x0000\r
-.equ UcodeHdrRevision, 0x0004\r
-.equ UcodeHdrDate, 0x0008\r
-.equ UcodeHdrProcessor, 0x000c\r
-.equ UcodeHdrChecksum, 0x0010\r
-.equ UcodeHdrLoader, 0x0014\r
-.equ UcodeHdrFlags, 0x0018\r
-.equ UcodeHdrDataSize, 0x001C\r
-.equ UcodeHdrTotalSize, 0x0020\r
-.equ UcodeHdrRsvd, 0x0024\r
-UcodeHdrEnd:\r
-.equ UcodeHdrLength, 0x0030 # UcodeHdrLength = UcodeHdrEnd - UcodeHdr\r
+\r
+MicrocodeHdr:\r
+.equ MicrocodeHdrVersion, 0x0000\r
+.equ MicrocodeHdrRevision, 0x0004\r
+.equ MicrocodeHdrDate, 0x0008\r
+.equ MicrocodeHdrProcessor, 0x000c\r
+.equ MicrocodeHdrChecksum, 0x0010\r
+.equ MicrocodeHdrLoader, 0x0014\r
+.equ MicrocodeHdrFlags, 0x0018\r
+.equ MicrocodeHdrDataSize, 0x001C\r
+.equ MicrocodeHdrTotalSize, 0x0020\r
+.equ MicrocodeHdrRsvd, 0x0024\r
+MicrocodeHdrEnd:\r
+.equ MicrocodeHdrLength, 0x0030 # MicrocodeHdrLength = MicrocodeHdrEnd - MicrocodeHdr\r
\r
\r
ExtSigHdr:\r
.equ ExtSigHdrCount, 0x0000\r
.equ ExtSigHdrChecksum, 0x0004\r
-.equ rsvd, 0x0008\r
+.equ ExtSigHdrRsvd, 0x0008\r
ExtSigHdrEnd:\r
.equ ExtSigHdrLength, 0x0014 #ExtSigHdrLength = ExtSigHdrEnd - ExtSigHdr\r
\r
ExtSigEnd:\r
.equ ExtSigLength, 0x000C #ExtSigLength = ExtSigEnd - ExtSig\r
\r
-LoadUcodeParams:\r
-.equ LoadUcodeParamsUcodeCodeAddr, 0x0000\r
-.equ LoadUcodeParamsUcodeCodeSize, 0x0004\r
-LoadUcodeParamsEnd:\r
+LoadMicrocodeParams:\r
+.equ MicrocodeCodeAddr, 0x0000\r
+.equ MicrocodeCodeSize, 0x0004\r
+LoadMicrocodeParamsEnd:\r
\r
-#.INCLUDE "UcodeLoadGcc.inc" - end\r
\r
-#.INCLUDE "SaveRestoreSseGcc.inc" - begin\r
\r
.macro SAVE_REGS\r
pinsrw $0x00, %ebp, %xmm7\r
.endm\r
\r
.macro ENABLE_SSE\r
- movl %cr4, %eax\r
- orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
- movl %eax,%cr4\r
+ jmp NextAddress\r
+.align 4\r
+ #\r
+ # Float control word initial value:\r
+ # all exceptions masked, double-precision, round-to-nearest\r
+ #\r
+ASM_PFX(mFpuControlWord): .word 0x027F\r
+ #\r
+ # Multimedia-extensions control word:\r
+ # all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+ #\r
+ASM_PFX(mMmxControlWord): .long 0x01F80\r
+SseError: \r
+ #\r
+ # Processor has to support SSE\r
+ #\r
+ jmp SseError \r
+NextAddress: \r
+ #\r
+ # Initialize floating point units\r
+ #\r
+ finit\r
+ fldcw ASM_PFX(mFpuControlWord)\r
+\r
+ #\r
+ # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+ # whether the processor supports SSE instruction.\r
+ #\r
+ movl $1, %eax\r
+ cpuid\r
+ btl $25, %edx\r
+ jnc SseError\r
+\r
+ #\r
+ # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
+ #\r
+ movl %cr4, %eax\r
+ orl $BIT9, %eax\r
+ movl %eax, %cr4\r
+\r
+ #\r
+ # The processor should support SSE instruction and we can use\r
+ # ldmxcsr instruction\r
+ #\r
+ ldmxcsr ASM_PFX(mMmxControlWord)\r
+.endm\r
+\r
+#Save in ECX-SLOT 3 in xmm6.\r
+.macro SAVE_EAX_MICROCODE_RET_STATUS\r
+ pinsrw $0x6, %eax, %xmm6\r
+ ror $0x10, %eax\r
+ pinsrw $0x7, %eax, %xmm6\r
+ rol $0x10, %eax\r
+.endm\r
+\r
+#Restore from ECX-SLOT 3 in xmm6.\r
+.macro LOAD_EAX_MICROCODE_RET_STATUS\r
+ pshufd $0x93, %xmm6, %xmm6\r
+ movd %xmm6, %eax\r
+ pshufd $0x39, %xmm6, %xmm6\r
.endm\r
\r
-#.INCLUDE "SaveRestoreSseGcc.inc" - end\r
\r
\r
#\r
.equ DATA_LEN_OF_MCUD, 0x018\r
.equ DATA_LEN_AT_STACK_TOP, (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
\r
-#------------------------------------------------------------------------------\r
-# FspSelfCheckDefault\r
-# Inputs:\r
-# eax -> Return address\r
-# Outputs:\r
-# eax -> 0 - Successful, Non-zero - Failed.\r
-# Register Usage:\r
-# eax is cleared and ebp is used for return address.\r
-# All others reserved.\r
-#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(FspSelfCheckDefault)\r
-ASM_PFX(FspSelfCheckDefault):\r
- #\r
- # Save return address to EBP\r
- #\r
- movl %eax, %ebp\r
- xorl %eax, %eax\r
-\r
-FspSelfCheckDefaultExit:\r
- jmp *%ebp\r
-\r
-\r
#------------------------------------------------------------------------------\r
# SecPlatformInitDefault\r
# Inputs:\r
\r
\r
#------------------------------------------------------------------------------\r
-# LoadUcode\r
+# LoadMicrocodeDefault\r
#\r
# Inputs:\r
-# esp -> LOAD_UCODE_PARAMS pointer\r
+# esp -> LoadMicrocodeParams pointer\r
# Register Usage:\r
# esp Preserved\r
# All others destroyed\r
# Executed by SBSP and NBSP\r
# Beginning of microcode update region starts on paragraph boundary\r
#------------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(LoadUcode)\r
-ASM_PFX(LoadUcode): \r
+ASM_GLOBAL ASM_PFX(LoadMicrocodeDefault)\r
+ASM_PFX(LoadMicrocodeDefault):\r
#\r
# Save return address to EBP\r
#\r
\r
cmpl $0x00, %esp\r
jz ParamError\r
- movl (%esp), %eax #dword ptr [] Parameter pointer\r
+ movl 4(%esp), %eax #dword ptr [] Parameter pointer\r
cmpl $0x00, %eax\r
jz ParamError\r
movl %eax, %esp\r
- movl LoadUcodeParamsUcodeCodeAddr(%esp), %esi #mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ movl MicrocodeCodeAddr(%esp), %esi\r
cmpl $0x00, %esi\r
jnz CheckMainHeader\r
\r
ParamError:\r
movl $0x080000002, %eax\r
- jmp LoadUcodeExit\r
+ jmp LoadMicrocodeExit\r
\r
CheckMainHeader:\r
#\r
# Minimal test checking for header version and loader version as 1\r
#\r
movl $0x01, %eax\r
- cmpl %eax, UcodeHdrVersion(%esi) #cmp [esi].ucode_hdr.version, eax\r
+ cmpl %eax, MicrocodeHdrVersion(%esi)\r
jne AdvanceFixedSize\r
- cmpl %eax, UcodeHdrLoader(%esi) #cmp [esi].ucode_hdr.loader, eax\r
+ cmpl %eax, MicrocodeHdrLoader(%esi)\r
jne AdvanceFixedSize\r
\r
#\r
# Check if signature and plaform ID match\r
#\r
- cmpl UcodeHdrProcessor(%esi), %ebx #cmp ebx, [esi].ucode_hdr.processor \r
- jne LoadUcodeL0\r
- testl UcodeHdrFlags(%esi), %edx #test edx, [esi].ucode_hdr.flags\r
+ cmpl MicrocodeHdrProcessor(%esi), %ebx\r
+ jne LoadMicrocodeL0\r
+ testl MicrocodeHdrFlags(%esi), %edx\r
jnz LoadCheck #Jif signature and platform ID match\r
\r
-LoadUcodeL0:\r
+LoadMicrocodeL0:\r
#\r
# Check if extended header exists\r
- # First check if total_size and data_size are valid\r
+ # First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
#\r
xorl %eax, %eax\r
- cmpl %eax, UcodeHdrTotalSize(%esi) #cmp [esi].ucode_hdr.total_size, eax\r
+ cmpl %eax, MicrocodeHdrTotalSize(%esi)\r
je NextMicrocode\r
- cmpl %eax, UcodeHdrDataSize(%esi) #cmp [esi].ucode_hdr.data_size, eax\r
+ cmpl %eax, MicrocodeHdrDataSize(%esi)\r
je NextMicrocode\r
\r
#\r
# Then verify total size - sizeof header > data size\r
#\r
- movl UcodeHdrTotalSize(%esi), %ecx #mov ecx, [esi].ucode_hdr.total_size\r
- subl $UcodeHdrLength, %ecx #sub ecx, sizeof ucode_hdr\r
- cmpl UcodeHdrDataSize(%esi), %ecx #cmp ecx, [esi].ucode_hdr.data_size\r
- jle NextMicrocode \r
+ movl MicrocodeHdrTotalSize(%esi), %ecx\r
+ subl $MicrocodeHdrLength, %ecx\r
+ cmpl MicrocodeHdrDataSize(%esi), %ecx\r
+ jle NextMicrocode\r
\r
#\r
# Set edi -> extended header\r
#\r
movl %esi, %edi\r
- addl $UcodeHdrLength, %edi #add edi, sizeof ucode_hdr\r
- addl UcodeHdrDataSize(%esi), %edi #add edi, [esi].ucode_hdr.data_size\r
+ addl $MicrocodeHdrLength, %edi\r
+ addl MicrocodeHdrDataSize(%esi), %edi\r
\r
#\r
# Get count of extended structures\r
#\r
- movl ExtSigHdrCount(%edi), %ecx #mov ecx, [edi].ext_sig_hdr.count\r
+ movl ExtSigHdrCount(%edi), %ecx\r
\r
#\r
# Move pointer to first signature structure\r
#\r
- addl ExtSigHdrLength, %edi #add edi, sizeof ext_sig_hdr\r
+ addl ExtSigHdrLength, %edi\r
\r
CheckExtSig:\r
#\r
# Check if extended signature and platform ID match\r
#\r
- cmpl %ebx, ExtSigProcessor(%edi) #cmp [edi].ext_sig.processor, ebx\r
- jne LoadUcodeL1\r
- test %edx, ExtSigFlags(%edi) #test [edi].ext_sig.flags, edx\r
+ cmpl %ebx, ExtSigProcessor(%edi)\r
+ jne LoadMicrocodeL1\r
+ test %edx, ExtSigFlags(%edi)\r
jnz LoadCheck # Jif signature and platform ID match\r
-LoadUcodeL1:\r
+LoadMicrocodeL1:\r
#\r
# Check if any more extended signatures exist\r
#\r
- addl $ExtSigLength, %edi #add edi, sizeof ext_sig\r
+ addl $ExtSigLength, %edi\r
loop CheckExtSig\r
\r
NextMicrocode:\r
# Advance just after end of this microcode\r
#\r
xorl %eax, %eax\r
- cmpl %eax, UcodeHdrTotalSize(%esi) #cmp [esi].ucode_hdr.total_size, eax\r
- je LoadUcodeL2\r
- addl UcodeHdrTotalSize(%esi), %esi #add esi, [esi].ucode_hdr.total_size\r
+ cmpl %eax, MicrocodeHdrTotalSize(%esi)\r
+ je LoadMicrocodeL2\r
+ addl MicrocodeHdrTotalSize(%esi), %esi\r
jmp CheckAddress\r
-LoadUcodeL2:\r
+LoadMicrocodeL2:\r
addl $0x800, %esi #add esi, dword ptr 2048\r
jmp CheckAddress\r
\r
#\r
# Is valid Microcode start point ?\r
#\r
- cmpl $0x0ffffffff, UcodeHdrVersion(%esi)\r
+ cmpl $0x0ffffffff, MicrocodeHdrVersion(%esi)\r
\r
#\r
# Is automatic size detection ?\r
#\r
- movl LoadUcodeParamsUcodeCodeSize(%esp), %eax\r
+ movl MicrocodeCodeSize(%esp), %eax\r
cmpl $0x0ffffffff, %eax\r
- jz LoadUcodeL3\r
+ jz LoadMicrocodeL3\r
#\r
# Address >= microcode region address + microcode region size?\r
#\r
- addl LoadUcodeParamsUcodeCodeAddr(%esp), %eax #mov eax, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ addl MicrocodeCodeAddr(%esp), %eax\r
\r
cmpl %eax, %esi\r
- jae Done #Jif address is outside of ucode region\r
+ jae Done #Jif address is outside of microcode region\r
jmp CheckMainHeader\r
\r
-LoadUcodeL3:\r
+LoadMicrocodeL3:\r
LoadCheck:\r
#\r
# Get the revision of the current microcode update loaded\r
#\r
# Verify this microcode update is not already loaded\r
#\r
- cmpl %edx, UcodeHdrRevision(%esi) #cmp [esi].ucode_hdr.revision, edx\r
+ cmpl %edx, MicrocodeHdrRevision(%esi)\r
je Continue\r
\r
-LoadMicrocode:\r
+LoadMicrocode0:\r
#\r
# EAX contains the linear address of the start of the Update Data\r
# EDX contains zero\r
# Start microcode load with wrmsr\r
#\r
movl %esi, %eax\r
- addl $UcodeHdrLength, %eax #add eax, sizeof ucode_hdr\r
+ addl $MicrocodeHdrLength, %eax\r
xorl %edx, %edx\r
movl $MSR_IA32_BIOS_UPDT_TRIG, %ecx\r
wrmsr\r
rdmsr # Get current microcode signature\r
xorl %eax, %eax\r
cmpl $0x00, %edx\r
- jnz LoadUcodeExit\r
+ jnz LoadMicrocodeExit\r
movl $0x08000000E, %eax\r
\r
-LoadUcodeExit:\r
+LoadMicrocodeExit:\r
jmp *%ebp\r
\r
\r
ASM_GLOBAL ASM_PFX(EstablishStackFsp)\r
ASM_PFX(EstablishStackFsp):\r
#\r
- # Save parameter pointer in edx \r
+ # Save parameter pointer in edx\r
#\r
movl 4(%esp), %edx\r
- \r
+\r
#\r
# Enable FSP STACK\r
#\r
pushl $0x4455434D # Signature of the data region 'MCUD'\r
pushl 12(%edx) # Code size\r
pushl 8(%edx) # Code base\r
- cmpl $0, %edx # Is parameter pointer valid ?\r
- jz InvalidMicrocodeRegion\r
pushl 4(%edx) # Microcode size\r
pushl (%edx) # Microcode base\r
- jmp EstablishStackFspExit\r
\r
-InvalidMicrocodeRegion:\r
- push $0 # Microcode size\r
- push $0 # Microcode base\r
- \r
-EstablishStackFspExit:\r
#\r
# Save API entry/exit timestamp into stack\r
#\r
\r
#\r
# Terminator for the data on stack\r
- # \r
+ #\r
push $0x00\r
\r
#\r
- # Set ECX/EDX to the bootloader temporary memory range\r
+ # Set ECX/EDX to the BootLoader temporary memory range\r
#\r
movl PcdGet32 (PcdTemporaryRamBase), %ecx\r
movl %ecx, %edx\r
subl PcdGet32 (PcdFspTemporaryRamSize), %edx\r
\r
xorl %eax, %eax\r
- \r
+\r
movd %mm7, %esi #RET_ESI\r
jmp *%esi\r
\r
\r
#\r
# CPUID/DeviceID check\r
- #\r
- movl $TempRamInitApiL0, %eax\r
- jmp ASM_PFX(FspSelfCheckDefault) # @note: ESP can not be changed.\r
-TempRamInitApiL0:\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
-\r
- #\r
- # Sec Platform Init\r
+ # and Sec Platform Init\r
#\r
movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit\r
- movd %mm7, %esi\r
+ movd %esi, %mm7\r
+ .weak ASM_PFX(SecPlatformInit)\r
+ .set ASM_PFX(SecPlatformInit), ASM_PFX(SecPlatformInitDefault)\r
jmp ASM_PFX(SecPlatformInit)\r
TempRamInitApiL1:\r
cmpl $0x00, %eax\r
# Load microcode\r
#\r
LOAD_ESP\r
- movl $TempRamInitApiL2, %esi #CALL_MMX LoadUcode\r
- movd %mm7, %esi\r
- jmp ASM_PFX(LoadUcode)\r
+ movl $TempRamInitApiL2, %esi #CALL_MMX LoadMicrocode\r
+ movd %esi, %mm7\r
+ .weak ASM_PFX(LoadMicrocode)\r
+ .set ASM_PFX(LoadMicrocode), ASM_PFX(LoadMicrocodeDefault)\r
+ jmp ASM_PFX(LoadMicrocode)\r
TempRamInitApiL2:\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
+ SAVE_EAX_MICROCODE_RET_STATUS #Save microcode return status in ECX-SLOT 3 in xmm6.\r
+ #@note If return value eax is not 0, microcode did not load, but continue and attempt to boot from ECX-SLOT 3 in xmm6.\r
\r
#\r
# Call Sec CAR Init\r
#\r
LOAD_ESP\r
movl $TempRamInitApiL3, %esi #CALL_MMX SecCarInit\r
- movd %mm7, %esi\r
+ movd %esi, %mm7\r
jmp ASM_PFX(SecCarInit)\r
TempRamInitApiL3:\r
cmpl $0x00, %eax\r
#\r
LOAD_ESP\r
movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp\r
- movd %mm7, %esi\r
+ movd %esi, %mm7\r
jmp ASM_PFX(EstablishStackFsp)\r
TempRamInitApiL4:\r
\r
+ LOAD_EAX_MICROCODE_RET_STATUS #Restore microcode status if no CAR init error.\r
+\r
NemInitExit:\r
#\r
# Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
LOAD_REGS\r
ret\r
\r
+\r
#----------------------------------------------------------------------------\r
# FspInit API\r
#\r
pushl %eax\r
\r
#\r
- # Pass the bootloader stack to SecStartup\r
+ # Pass the BootLoader stack to SecStartup\r
#\r
pushl %edi\r
\r
FspApiCommonExit:\r
ret\r
\r
-\r
--- /dev/null
+;; @file\r
+; Provide FSP helper function.\r
+;\r
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;;\r
+\r
+ .586p\r
+ .model flat,C\r
+ .code\r
+\r
+FspInfoHeaderRelativeOff PROC NEAR PRIVATE\r
+ ;\r
+ ; This value will be pached by the build script\r
+ ;\r
+ DD 012345678h\r
+FspInfoHeaderRelativeOff ENDP\r
+\r
+GetFspBaseAddress PROC NEAR PUBLIC\r
+ mov eax, GetFspBaseAddress\r
+ sub eax, dword ptr [FspInfoHeaderRelativeOff]\r
+ add eax, 01Ch\r
+ mov eax, dword ptr [eax]\r
+ ret\r
+GetFspBaseAddress ENDP\r
+\r
+ END
\ No newline at end of file
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Abstract:\r
+#\r
+# Provide FSP helper function.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(FspInfoHeaderRelativeOff)\r
+ASM_PFX(FspInfoHeaderRelativeOff):\r
+ #\r
+ # This value will be pached by the build script\r
+ #\r
+ .long 0x012345678\r
+\r
+\r
+ASM_GLOBAL ASM_PFX(GetFspBaseAddress)\r
+ASM_PFX(GetFspBaseAddress):\r
+ mov $GetFspBaseAddress, %eax\r
+ sub $FspInfoHeaderRelativeOff, %eax\r
+ add $0x01C, %eax\r
+ mov (%eax), %eax\r
+ ret\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Abstract:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+MSR_IA32_PLATFORM_ID EQU 000000017h\r
+MSR_IA32_BIOS_UPDT_TRIG EQU 000000079h\r
+MSR_IA32_BIOS_SIGN_ID EQU 00000008bh\r
+\r
+\r
+MicrocodeHdr STRUCT 1t\r
+ MicrocodeHdrVersion DWORD ?\r
+ MicrocodeHdrRevision DWORD ?\r
+ MicrocodeHdrDate DWORD ?\r
+ MicrocodeHdrProcessor DWORD ?\r
+ MicrocodeHdrChecksum DWORD ?\r
+ MicrocodeHdrLoader DWORD ?\r
+ MicrocodeHdrFlags DWORD ?\r
+ MicrocodeHdrDataSize DWORD ?\r
+ MicrocodeHdrTotalSize DWORD ?\r
+ MicrocodeHdrRsvd DWORD 3t DUP (?)\r
+MicrocodeHdr ENDS\r
+\r
+ExtSigHdr STRUCT 1t\r
+ ExtSigHdrCount DWORD ?\r
+ ExtSigHdrChecksum DWORD ?\r
+ ExtSigHdrRsvd DWORD 3t DUP (?)\r
+ExtSigHdr ENDS\r
+\r
+ExtSig STRUCT 1t\r
+ ExtSigProcessor DWORD ?\r
+ ExtSigFlags DWORD ?\r
+ ExtSigChecksum DWORD ?\r
+ExtSig ENDS\r
+\r
+LoadMicrocodeParams STRUCT 1t\r
+ MicrocodeCodeAddr DWORD ?\r
+ MicrocodeCodeSize DWORD ?\r
+LoadMicrocodeParams ENDS\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
ENDM\r
ENDIF\r
\r
-\r
+;\r
+; XMM7 to save/restore EBP, EBX, ESI, EDI\r
+; \r
SAVE_REGS MACRO\r
SXMMN xmm7, 0, ebp\r
SXMMN xmm7, 1, ebx\r
LOAD_ESP\r
ENDM\r
\r
+;\r
+; XMM6 to save/restore EAX, EDX, ECX, ESP\r
+; \r
LOAD_EAX MACRO\r
LXMMN xmm6, eax, 1\r
ENDM\r
LOAD_ESP MACRO\r
movd esp, xmm6\r
ENDM\r
-\r
-ENABLE_SSE MACRO\r
- mov eax, cr4\r
- or eax, 00000600h\r
- mov cr4, eax\r
+ \r
+;\r
+; XMM5 for calling stack\r
+;\r
+CALL_XMM MACRO Entry\r
+ local ReturnAddress\r
+ mov esi, offset ReturnAddress\r
+ pslldq xmm5, 4\r
+IFDEF USE_SSE41_FLAG\r
+ pinsrd xmm5, esi, 0\r
+ELSE \r
+ pinsrw xmm5, esi, 0\r
+ ror esi, 16\r
+ pinsrw xmm5, esi, 1 \r
+ENDIF \r
+ mov esi, Entry\r
+ jmp esi\r
+ReturnAddress: \r
ENDM\r
+ \r
+RET_XMM MACRO \r
+ movd esi, xmm5\r
+ psrldq xmm5, 4\r
+ jmp esi\r
+ ENDM\r
+ \r
+ENABLE_SSE MACRO\r
+ ;\r
+ ; Initialize floating point units\r
+ ;\r
+ local NextAddress \r
+ jmp NextAddress\r
+ALIGN 4\r
+ ;\r
+ ; Float control word initial value:\r
+ ; all exceptions masked, double-precision, round-to-nearest\r
+ ;\r
+FpuControlWord DW 027Fh\r
+ ;\r
+ ; Multimedia-extensions control word:\r
+ ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
+ ;\r
+MmxControlWord DD 01F80h \r
+SseError: \r
+ ;\r
+ ; Processor has to support SSE\r
+ ;\r
+ jmp SseError \r
+NextAddress: \r
+ finit\r
+ fldcw FpuControlWord\r
+\r
+ ;\r
+ ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+ ; whether the processor supports SSE instruction.\r
+ ;\r
+ mov eax, 1\r
+ cpuid\r
+ bt edx, 25\r
+ jnc SseError\r
+\r
+IFDEF USE_SSE41_FLAG\r
+ ;\r
+ ; SSE 4.1 support\r
+ ;\r
+ bt ecx, 19 \r
+ jnc SseError\r
+ENDIF\r
+\r
+ ;\r
+ ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
+ ;\r
+ mov eax, cr4\r
+ or eax, 00000600h\r
+ mov cr4, eax\r
+\r
+ ;\r
+ ; The processor should support SSE instruction and we can use\r
+ ; ldmxcsr instruction\r
+ ;\r
+ ldmxcsr MmxControlWord\r
+ ENDM\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-;\r
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Abstract:\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-MSR_IA32_PLATFORM_ID EQU 000000017h\r
-MSR_IA32_BIOS_UPDT_TRIG EQU 000000079h\r
-MSR_IA32_BIOS_SIGN_ID EQU 00000008bh\r
-\r
-ucode STRUCT 1t\r
- version DWORD ?\r
- revision DWORD ?\r
- date DWORD ?\r
- processor DWORD ?\r
- checksum DWORD ?\r
- loader DWORD ?\r
- rsvd DWORD 6t DUP (?)\r
- data DWORD 500t DUP (?)\r
-ucode ENDS\r
-ucode_t TYPEDEF ucode\r
-\r
-ucode_hdr STRUCT 1t\r
- version DWORD ?\r
- revision DWORD ?\r
- date DWORD ?\r
- processor DWORD ?\r
- checksum DWORD ?\r
- loader DWORD ?\r
- flags DWORD ?\r
- data_size DWORD ?\r
- total_size DWORD ?\r
- rsvd DWORD 3t DUP (?)\r
-ucode_hdr ENDS\r
-ucode_hdr_t TYPEDEF ucode_hdr\r
-\r
-ext_sig_hdr STRUCT 1t\r
- count DWORD ?\r
- checksum DWORD ?\r
- rsvd DWORD 3t DUP (?)\r
-ext_sig_hdr ENDS\r
-ext_sig_hdr_t TYPEDEF ext_sig_hdr\r
-\r
-ext_sig STRUCT 1t\r
- processor DWORD ?\r
- flags DWORD ?\r
- checksum DWORD ?\r
-ext_sig ENDS\r
-ext_sig_t TYPEDEF ext_sig\r
-\r
-LOAD_UCODE_PARAMS STRUCT 1t\r
- ucode_code_addr DWORD ?\r
- ucode_code_size DWORD ?\r
-LOAD_UCODE_PARAMS ENDS\r
TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);\r
\r
FspPlatformData->DataPtr = NULL;\r
- FspPlatformData->CodeRegionSize = 0;\r
+ FspPlatformData->MicrocodeRegionBase = 0;\r
+ FspPlatformData->MicrocodeRegionSize = 0;\r
FspPlatformData->CodeRegionBase = 0;\r
- FspPlatformData->MicorcodeRegionBase = 0;\r
- FspPlatformData->MicorcodeRegionSize = 0;\r
+ FspPlatformData->CodeRegionSize = 0;\r
\r
//\r
// Pointer to the size field\r
//\r
DwordSize = 4;\r
StackPtr = StackPtr - 1 - DwordSize;\r
- CopyMem (&(FspPlatformData->CodeRegionBase), StackPtr, (DwordSize << 2));\r
+ CopyMem (&(FspPlatformData->MicrocodeRegionBase), StackPtr, (DwordSize << 2));\r
StackPtr--;\r
} else if (*(StackPtr - 1) == FSP_PER0_SIGNATURE) {\r
//\r
It needs to be done as soon as possible after the stack is setup.\r
\r
@param[in,out] PeiFspData Pointer of the FSP global data.\r
- @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] BootLoaderStack BootLoader stack.\r
@param[in] ApiIdx The index of the FSP API.\r
\r
**/\r
VOID\r
FspGlobalDataInit (\r
IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
- IN UINT32 BootloaderStack,\r
+ IN UINT32 BootLoaderStack,\r
IN UINT8 ApiIdx\r
)\r
{\r
ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA));\r
\r
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;\r
- PeiFspData->CoreStack = BootloaderStack;\r
+ PeiFspData->CoreStack = BootLoaderStack;\r
PeiFspData->PerfIdx = 2;\r
\r
SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_ENTRY);\r
This function check the FSP API calling condition.\r
\r
@param[in] ApiIdx Internal index of the FSP API.\r
+ @param[in] ApiParam Parameter of the FSP API.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
FspApiCallingCheck (\r
- UINT32 ApiIdx\r
+ IN UINT32 ApiIdx,\r
+ IN VOID *ApiParam\r
)\r
{\r
- EFI_STATUS Status;\r
- FSP_GLOBAL_DATA *FspData;\r
+ EFI_STATUS Status;\r
+ FSP_GLOBAL_DATA *FspData;\r
+ FSP_INIT_PARAMS *FspInitParams;\r
+ FSP_INIT_RT_COMMON_BUFFER *FspRtBuffer;\r
+\r
+ FspInitParams = (FSP_INIT_PARAMS *) ApiParam;\r
+ FspRtBuffer = ((FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr);\r
\r
Status = EFI_SUCCESS;\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
if (ApiIdx == 1) {\r
//\r
// FspInit check\r
//\r
if ((UINT32)FspData != 0xFFFFFFFF) {\r
Status = EFI_UNSUPPORTED;\r
+ } else if ((FspRtBuffer == NULL) || ((FspRtBuffer->BootLoaderTolumSize % EFI_PAGE_SIZE) != 0)) {\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
} else if (ApiIdx == 2) {\r
//\r
//\r
if ((UINT32)FspData != 0xFFFFFFFF) {\r
Status = EFI_UNSUPPORTED;\r
+ } else if ((FspRtBuffer == NULL) || ((FspRtBuffer->BootLoaderTolumSize % EFI_PAGE_SIZE) != 0)) {\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
} else if (ApiIdx == 4) {\r
//\r
\r
return Status;\r
}\r
+\r
+/**\r
+ This function gets the boot FV offset in FSP.\r
+ @return the boot firmware volumen offset inside FSP binary\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetBootFirmwareVolumeOffset (\r
+ VOID\r
+ )\r
+{ \r
+ return PcdGet32 (PcdFspBootFirmwareVolumeBase) - PcdGet32 (PcdFspAreaBaseAddress);\r
+}\r
It needs to be done as soon as possible after the stack is setup.\r
\r
@param[in,out] PeiFspData Pointer of the FSP global data.\r
- @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] BootLoaderStack BootLoader stack.\r
@param[in] ApiIdx The index of the FSP API.\r
\r
**/\r
VOID\r
FspGlobalDataInit (\r
IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
- IN UINT32 BootloaderStack,\r
+ IN UINT32 BootLoaderStack,\r
IN UINT8 ApiIdx\r
);\r
\r
@param[in] TempRamBase Base address of tempory ram\r
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
@param[in] PeiCore PeiCore entry point.\r
- @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] BootLoaderStack BootLoader stack.\r
@param[in] ApiIdx the index of API.\r
\r
@return This function never returns.\r
IN UINT32 TempRamBase,\r
IN VOID *BootFirmwareVolume,\r
IN PEI_CORE_ENTRY PeiCore,\r
- IN UINT32 BootloaderStack,\r
+ IN UINT32 BootLoaderStack,\r
IN UINT32 ApiIdx\r
)\r
{\r
//\r
// Iniitalize the global FSP data region\r
//\r
- FspGlobalDataInit (&PeiFspData, BootloaderStack, (UINT8)ApiIdx);\r
+ FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);\r
\r
//\r
// Update the base address and length of Pei temporary memory\r
@param[in] TempRamBase Base address of tempory ram\r
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
@param[in] PeiCore PeiCore entry point.\r
- @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] BootLoaderStack BootLoader stack.\r
@param[in] ApiIdx the index of API.\r
\r
@return This function never returns.\r
IN UINT32 TempRamBase,\r
IN VOID *BootFirmwareVolume,\r
IN PEI_CORE_ENTRY PeiCore,\r
- IN UINT32 BootloaderStack,\r
+ IN UINT32 BootLoaderStack,\r
IN UINT32 ApiIdx\r
);\r
\r
/// User platform configuraiton data region pointer.\r
///\r
VOID *UpdDataRgnPtr;\r
+ //\r
+ // Below field is added in FSP EAS v1.1\r
+ //\r
+ ///\r
+ /// The size of memory to be reserved below the top of low usable memory (TOLUM)\r
+ /// for BootLoader usage. This is optional and value can be zero. If non-zero, the\r
+ /// size must be a multiple of 4KB.\r
+ ///\r
+ UINT32 BootLoaderTolumSize;\r
///\r
/// Reserved\r
///\r
- UINT32 Reserved[7];\r
+ UINT32 Reserved[6];\r
} FSP_INIT_RT_COMMON_BUFFER;\r
\r
typedef enum {\r
and defined for each FSP binary. This will be documented in Integration guide with\r
each FSP release.\r
After FspMemInit completes its execution, it passes the pointer to the HobList and\r
- returns to the boot loader from where it was called. Bootloader is responsible to \r
+ returns to the boot loader from where it was called. BootLoader is responsible to \r
migrate it's stack and data to Memory.\r
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
complete the silicon initialization and provides bootloader an opportunity to get\r
///\r
UINT32 ImageSize;\r
///\r
- /// Byte 0x18: FSP binary preferred base address\r
+ /// Byte 0x1C: FSP binary preferred base address\r
///\r
UINT32 ImageBase;\r
\r
///\r
UINT32 CfgRegionOffset;\r
///\r
- /// Byte 0x24: Size of the FSP configuration region\r
+ /// Byte 0x28: Size of the FSP configuration region\r
///\r
UINT32 CfgRegionSize;\r
///\r
UINT32 NotifyPhaseEntryOffset;\r
\r
///\r
- /// Below field is added in FSP 1.1\r
+ /// Below fields are added in FSP Revision 2\r
///\r
\r
///\r
} FSP_INFO_HEADER;\r
\r
///\r
-/// Below structure is added in FSP 1.1\r
+/// Below structure is added in FSP version 2\r
///\r
typedef struct {\r
///\r
\r
extern EFI_GUID gFspBootLoaderTemporaryMemoryGuid;\r
\r
+extern EFI_GUID gFspBootLoaderTolumHobGuid; // FSP EAS v1.1\r
extern EFI_GUID gFspReservedMemoryResourceHobGuid;\r
extern EFI_GUID gFspNonVolatileStorageHobGuid;\r
\r
);\r
\r
/**\r
- This function changes the Bootloader return address in stack.\r
+ This function changes the BootLoader return address in stack.\r
\r
@param[in] ReturnAddress Address to return.\r
\r
);\r
\r
/**\r
- This function set the API status code returned to the bootloader.\r
+ This function set the API status code returned to the BootLoader.\r
\r
@param[in] ReturnStatus Status code to return.\r
\r
VOID\r
);\r
\r
+/**\r
+ This function gets the VPD data pointer.\r
+\r
+ @return VpdDataRgnPtr VPD data pointer.\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetFspVpdDataPointer (\r
+ VOID\r
+ );\r
+\r
/**\r
This function gets FSP API calling mode.\r
\r
);\r
\r
/**\r
- Migrate bootloader data before destroying CAR.\r
+ Migrate BootLoader data before destroying CAR.\r
\r
**/\r
VOID\r
\r
/**\r
This function transfer control to the ContinuationFunc passed in by the\r
- bootloader.\r
+ BootLoader.\r
\r
**/\r
VOID\r
);\r
\r
/**\r
- This function handle NotifyPhase API call from the bootloader.\r
- It gives control back to the bootloader after it is handled. If the\r
+ This function handle NotifyPhase API call from the BootLoader.\r
+ It gives control back to the BootLoader after it is handled. If the\r
Notification code is a ReadyToBoot event, this function will return\r
and FSP continues the remaining execution until it reaches the DxeIpl.\r
\r
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FSP_SEC_PLATFORM_LIB_H_\r
+#define _FSP_SEC_PLATFORM_LIB_H_\r
+\r
+/**\r
+ This function performs platform level initialization.\r
+\r
+ This function must be in ASM file, because stack is not established yet.\r
+ This function is optional. If a library instance does not provide this function, the default empty one will be used.\r
+\r
+ The callee should not use XMM6/XMM7.\r
+ The return address is saved in MM7.\r
+\r
+ @retval in saved in EAX - 0 means platform initialization success.\r
+ other means platform initialization fail.\r
+**/\r
+UINT32\r
+EFIAPI\r
+SecPlatformInit (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function loads Microcode.\r
+\r
+ This function must be in ASM file, because stack is not established yet.\r
+ This function is optional. If a library instance does not provide this function, the default one will be used.\r
+\r
+ The callee should not use XMM6/XMM7.\r
+ The return address is saved in MM7.\r
+\r
+ @param TempRamInitParamPtr A data structure to hold microcode parameter. It is saved in ESP.\r
+\r
+ @retval in saved in EAX - 0 means Microcode is loaded successfully.\r
+ other means Microcode is not loaded successfully.\r
+**/\r
+UINT32\r
+EFIAPI\r
+LoadMicrocode (\r
+ IN FSP_TEMP_RAM_INIT_PARAMS *TempRamInitParamPtr\r
+ );\r
+\r
+/**\r
+ This function initializes the CAR.\r
+\r
+ This function must be in ASM file, because stack is not established yet.\r
+\r
+ The callee should not use XMM6/XMM7.\r
+ The return address is saved in MM7.\r
+\r
+ @param TempRamInitParamPtr A data structure to hold microcode parameter. It is saved in ESP.\r
+\r
+ @retval in saved in EAX - 0 means CAR initialization success.\r
+ other means CAR initialization fail.\r
+**/\r
+UINT32\r
+EFIAPI\r
+SecCarInit (\r
+ IN FSP_TEMP_RAM_INIT_PARAMS *TempRamInitParamPtr\r
+ );\r
+\r
+#endif\r
\r
typedef struct {\r
VOID *DataPtr;\r
+ UINT32 MicrocodeRegionBase;\r
+ UINT32 MicrocodeRegionSize;\r
UINT32 CodeRegionBase;\r
UINT32 CodeRegionSize;\r
- UINT32 MicorcodeRegionBase;\r
- UINT32 MicorcodeRegionSize;\r
} FSP_PLAT_DATA;\r
\r
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')\r
\r
[LibraryClasses]\r
## @libraryclass Provides cache-as-ram support.\r
- CacheAsRamLib|IntelFspPkg/Include/Library/CacheAsRamLib.h\r
+ CacheAsRamLib|Include/Library/CacheAsRamLib.h\r
\r
## @libraryclass Provides cache setting on MTRR.\r
- CacheLib|IntelFspPkg/Include/Library/CacheLib.h\r
+ CacheLib|Include/Library/CacheLib.h\r
\r
## @libraryclass Provides debug device abstraction.\r
- DebugDeviceLib|IntelFspPkg/Include/Library/DebugDeviceLib.h\r
+ DebugDeviceLib|Include/Library/DebugDeviceLib.h\r
\r
## @libraryclass Provides FSP related services.\r
- FspCommonLib|IntelFspPkg/Include/Library/FspCommonLib.h\r
+ FspCommonLib|Include/Library/FspCommonLib.h\r
\r
## @libraryclass Provides FSP platform related actions.\r
- FspPlatformLib|IntelFspPkg/Include/Library/FspPlatformLib.h\r
+ FspPlatformLib|Include/Library/FspPlatformLib.h\r
\r
## @libraryclass Provides FSP switch stack function.\r
- FspSwitchStackLib|IntelFspPkg/Include/Library/FspSwitchStackLib.h\r
+ FspSwitchStackLib|Include/Library/FspSwitchStackLib.h\r
+ \r
+ ## @libraryclass Provides FSP platform sec related actions.\r
+ FspSecPlatformLib|Include/Library/FspSecPlatformLib.h\r
\r
[Guids]\r
#\r
gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
+ gFspBootLoaderTolumHobGuid = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1\r
\r
# Guid defined by platform\r
gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }\r
gFspReservedMemoryResourceHobMiscGuid = { 0x00d6b14b, 0x7dd0, 0x4062, { 0x88, 0x21, 0xe5, 0xf9, 0x6a, 0x2a, 0x1b, 0x00 } }\r
\r
[PcdsFixedAtBuild]\r
- gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00108|UINT32|0x00000001\r
- gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001\r
- gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002\r
- gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003\r
- gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001\r
- gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry | 5|UINT32|0x00002002\r
+ gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001\r
+ gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001\r
+ gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry | 6|UINT32|0x00002002\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress |0xFFF80000|UINT32|0x10000001\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize |0x00040000|UINT32|0x10000002\r
+ gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
\r
[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
gIntelFspPkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r
FspCommonLib|IntelFspPkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf\r
FspPlatformLib|IntelFspPkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf\r
FspSwitchStackLib|IntelFspPkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf\r
+ FspSecPlatformLib|IntelFspPkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf\r
\r
[LibraryClasses.common.PEIM]\r
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
IntelFspPkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf\r
IntelFspPkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf\r
\r
- IntelFspPkg/FspSecCore/FspSecCore.inf {\r
- <LibraryClasses>\r
- NULL|IntelFspPkg/Library/SecPlatformSecLibNull/SecPlatformSecLibNull.inf\r
- }\r
+ IntelFspPkg/FspSecCore/FspSecCore.inf\r
IntelFspPkg/FspDxeIpl/FspDxeIpl.inf\r
\r
[PcdsFixedAtBuild.common]\r
\r
\r
/**\r
- This function changes the Bootloader return address in stack.\r
+ This function changes the BootLoader return address in stack.\r
\r
@param[in] ReturnAddress Address to return.\r
\r
}\r
\r
/**\r
- This function set the API status code returned to the bootloader.\r
+ This function set the API status code returned to the BootLoader.\r
\r
@param[in] ReturnStatus Status code to return.\r
\r
return GetFspGlobalDataPointer()->FspInfoHeader;\r
}\r
\r
+/**\r
+ This function gets the VPD data pointer.\r
+\r
+ @return VpdDataRgnPtr VPD data pointer.\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetFspVpdDataPointer (\r
+ VOID\r
+ )\r
+{\r
+ FSP_INFO_HEADER *FspInfoHeader;\r
+\r
+ FspInfoHeader = GetFspInfoHeader ();\r
+ return (VOID *)(FspInfoHeader->ImageBase + FspInfoHeader->CfgRegionOffset);\r
+}\r
+\r
/**\r
This function gets FSP API calling mode.\r
\r
}\r
\r
/**\r
- Migrate bootloader data before destroying CAR.\r
+ Migrate BootLoader data before destroying CAR.\r
\r
**/\r
VOID\r
ApiMode = GetFspApiCallingMode ();\r
\r
//\r
- // Get the temporary memory range used by the bootloader\r
+ // Get the temporary memory range used by the BootLoader\r
//\r
BootLoaderTempRamStart = PcdGet32(PcdTemporaryRamBase);\r
BootLoaderTempRamSize = PcdGet32(PcdTemporaryRamSize) - PcdGet32(PcdFspTemporaryRamSize);\r
\r
/**\r
This function transfer control to the ContinuationFunc passed in by the\r
- bootloader.\r
+ BootLoader.\r
\r
**/\r
VOID\r
FSP_INIT_PARAMS *FspInitParams;\r
\r
if (GetFspApiCallingMode() == 0) {\r
- //\r
- // FspInit API is used, so jump into the ContinuationFunc\r
- //\r
+ //\r
+ // FspInit API is used, so jump into the ContinuationFunc\r
+ //\r
FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();\r
\r
//\r
}\r
\r
/**\r
- This function handle NotifyPhase API call from the bootloader.\r
- It gives control back to the bootloader after it is handled. If the\r
+ This function handle NotifyPhase API call from the BootLoader.\r
+ It gives control back to the BootLoader after it is handled. If the\r
Notification code is a ReadyToBoot event, this function will return\r
and FSP continues the remaining execution until it reaches the DxeIpl.\r
\r
--- /dev/null
+;; @file\r
+; This is the code that goes from real-mode to protected mode.\r
+; It consumes the reset vector, configures the stack.\r
+;\r
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;;\r
+\r
+;\r
+; Define assembler characteristics\r
+;\r
+.586p\r
+.xmm\r
+.model flat, c\r
+\r
+EXTRN TempRamInitApi:NEAR\r
+EXTRN FspInitApi:NEAR\r
+\r
+;\r
+; Contrary to the name, this file contains 16 bit code as well.\r
+;\r
+_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'\r
+ ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: _ModuleEntryPoint\r
+;\r
+; Input: None\r
+;\r
+; Output: None\r
+;\r
+; Destroys: Assume all registers\r
+;\r
+; Description:\r
+;\r
+; Transition to non-paged flat-model protected mode from a\r
+; hard-coded GDT that provides exactly two descriptors.\r
+; This is a bare bones transition to protected mode only\r
+; used for a while in PEI and possibly DXE.\r
+;\r
+; After enabling protected mode, a far jump is executed to\r
+; transfer to PEI using the newly loaded GDT.\r
+;\r
+; Return: None\r
+;\r
+;----------------------------------------------------------------------------\r
+align 16\r
+_ModuleEntryPoint PROC C PUBLIC\r
+ ;\r
+ ; Load the GDT table in GdtDesc\r
+ ;\r
+ mov esi, OFFSET GdtDesc\r
+ db 66h\r
+ lgdt fword ptr cs:[si]\r
+\r
+ ;\r
+ ; Transition to 16 bit protected mode\r
+ ;\r
+ mov eax, cr0 ; Get control register 0\r
+ or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)\r
+ mov cr0, eax ; Activate protected mode\r
+\r
+ ;\r
+ ; Now we're in 16 bit protected mode\r
+ ; Set up the selectors for 32 bit protected mode entry\r
+ ; \r
+ mov ax, SYS_DATA_SEL\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+ mov ss, ax\r
+\r
+ ;\r
+ ; Transition to Flat 32 bit protected mode\r
+ ; The jump to a far pointer causes the transition to 32 bit mode\r
+ ;\r
+ mov esi, offset ProtectedModeEntryLinearAddress\r
+ jmp fword ptr cs:[si]\r
+\r
+_ModuleEntryPoint ENDP\r
+\r
+_TEXT_REALMODE ENDS\r
+\r
+.code \r
+;\r
+; Protected mode portion initializes stack, configures cache, and calls C entry point\r
+;\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: ProtectedModeEntryPoint\r
+;\r
+; Input: Executing in 32 Bit Protected (flat) mode\r
+; cs: 0-4GB\r
+; ds: 0-4GB\r
+; es: 0-4GB\r
+; fs: 0-4GB\r
+; gs: 0-4GB\r
+; ss: 0-4GB\r
+;\r
+; Output: This function never returns\r
+;\r
+; Destroys:\r
+; ecx\r
+; edi\r
+; esi\r
+; esp\r
+;\r
+; Description:\r
+; Perform any essential early platform initilaisation\r
+; Setup a stack\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+ProtectedModeEntryPoint PROC NEAR C PUBLIC\r
+ ;\r
+ ; Dummy function. Consume 2 API to make sure they can be linked.\r
+ ;\r
+ mov eax, TempRamInitApi\r
+ mov eax, FspInitApi\r
+\r
+ ; Should never return\r
+ jmp $\r
+\r
+ProtectedModeEntryPoint ENDP\r
+\r
+;\r
+; ROM-based Global-Descriptor Table for the PEI Phase\r
+;\r
+align 16\r
+PUBLIC BootGdtTable\r
+\r
+;\r
+; GDT[0]: 0x00: Null entry, never used.\r
+;\r
+NULL_SEL equ $ - GDT_BASE ; Selector [0]\r
+GDT_BASE:\r
+BootGdtTable DD 0\r
+ DD 0\r
+;\r
+; Linear code segment descriptor\r
+;\r
+LINEAR_CODE_SEL equ $ - GDT_BASE ; Selector [0x8]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 09Bh ; present, ring 0, data, expand-up, not-writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; System data segment descriptor\r
+;\r
+SYS_DATA_SEL equ $ - GDT_BASE ; Selector [0x10]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 093h ; present, ring 0, data, expand-up, not-writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+\r
+GDT_SIZE EQU $ - BootGDTtable ; Size, in bytes\r
+\r
+;\r
+; GDT Descriptor\r
+;\r
+GdtDesc: ; GDT descriptor\r
+ DW GDT_SIZE - 1 ; GDT limit\r
+ DD OFFSET BootGdtTable ; GDT base address\r
+\r
+ProtectedModeEntryLinearAddress LABEL FWORD\r
+ProtectedModeEntryLinearOffset LABEL DWORD\r
+ DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code\r
+ DW LINEAR_CODE_SEL\r
+ \r
+END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Abstract:\r
+#\r
+# This is the code that goes from real-mode to protected mode.\r
+# It consumes the reset vector, configures the stack.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+\r
+#\r
+# Contrary to the name, this file contains 16 bit code as well.\r
+#\r
+.text\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: _ModuleEntryPoint\r
+#\r
+# Input: None\r
+#\r
+# Output: None\r
+#\r
+# Destroys: Assume all registers\r
+#\r
+# Description:\r
+#\r
+# Transition to non-paged flat-model protected mode from a\r
+# hard-coded GDT that provides exactly two descriptors.\r
+# This is a bare bones transition to protected mode only\r
+# used for a while in PEI and possibly DXE.\r
+#\r
+# After enabling protected mode, a far jump is executed to\r
+# transfer to PEI using the newly loaded GDT.\r
+#\r
+# Return: None\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)\r
+ASM_PFX(_ModuleEntryPoint):\r
+\r
+ #\r
+ # Load the GDT table in GdtDesc\r
+ #\r
+ .byte 0x66,0xbe #movl $GdtDesc, %esi\r
+ .long GdtDesc\r
+ \r
+ .byte 0x66,0x2e,0x0f,0x01,0x14 #lgdt %cs:(%si)\r
+\r
+ #\r
+ # Transition to 16 bit protected mode\r
+ #\r
+ .byte 0x0f,0x20,0xc0 #movl %cr0, %eax # Get control register 0\r
+ .byte 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)\r
+ .byte 0x0f,0x22,0xc0 #movl %eax, %cr0 # Activate protected mode\r
+\r
+ #\r
+ # Now we're in 16 bit protected mode\r
+ # Set up the selectors for 32 bit protected mode entry\r
+ # \r
+ .byte 0xb8 #movw SYS_DATA_SEL, %ax\r
+ .word SYS_DATA_SEL\r
+ \r
+ .byte 0x8e,0xd8 #movw %ax, %ds\r
+ .byte 0x8e,0xc0 #movw %ax, %es\r
+ .byte 0x8e,0xe0 #movw %ax, %fs\r
+ .byte 0x8e,0xe8 #movw %ax, %gs\r
+ .byte 0x8e,0xd0 #movw %ax, %ss\r
+\r
+ #\r
+ # Transition to Flat 32 bit protected mode\r
+ # The jump to a far pointer causes the transition to 32 bit mode\r
+ #\r
+ .byte 0x66,0xbe #movl ProtectedModeEntryLinearAddress, %esi\r
+ .long ProtectedModeEntryLinearAddress \r
+ .byte 0x66,0x2e,0xff,0x2c #jmp %cs:(%esi)\r
+\r
+#\r
+# Protected mode portion initializes stack, configures cache, and calls C entry point\r
+#\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: ProtectedModeEntryPoint\r
+#\r
+# Input: Executing in 32 Bit Protected (flat) mode\r
+# cs: 0-4GB\r
+# ds: 0-4GB\r
+# es: 0-4GB\r
+# fs: 0-4GB\r
+# gs: 0-4GB\r
+# ss: 0-4GB\r
+#\r
+# Output: This function never returns\r
+#\r
+# Destroys:\r
+# ecx\r
+# edi\r
+# esi\r
+# esp\r
+#\r
+# Description:\r
+# Perform any essential early platform initilaisation\r
+# Setup a stack\r
+#\r
+#----------------------------------------------------------------------------\r
+ProtectedModeEntryPoint:\r
+ #\r
+ # Dummy function. Consume 2 API to make sure they can be linked.\r
+ #\r
+ movl ASM_PFX(TempRamInitApi), %eax\r
+ movl ASM_PFX(FspInitApi), %eax\r
+ #\r
+ # Should never return\r
+ #\r
+ jmp . #'$'\r
+\r
+#\r
+# ROM-based Global-Descriptor Table for the PEI Phase\r
+#\r
+.align 16\r
+#\r
+# GDT[0]: 000h: Null entry, never used.\r
+#\r
+.equ NULL_SEL, . - GDT_BASE # Selector [0]\r
+GDT_BASE: \r
+BootGdtTable: \r
+ .long 0\r
+ .long 0\r
+#\r
+# Linear code segment descriptor\r
+#\r
+.equ LINEAR_CODE_SEL, . - GDT_BASE # Selector [08h]\r
+ .word 0xFFFF # limit 0FFFFh\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x9B # present, ring 0, data, expand-up, not-writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+#\r
+# System data segment descriptor\r
+#\r
+.equ SYS_DATA_SEL, . - GDT_BASE # Selector [010h]\r
+ .word 0xFFFF # limit 0FFFFh\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x93 # present, ring 0, data, expand-up, not-writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+\r
+.equ GDT_SIZE, . - BootGdtTable # Size, in bytes\r
+\r
+#\r
+# GDT Descriptor\r
+#\r
+GdtDesc: # GDT descriptor\r
+ .word GDT_SIZE - 1 \r
+ .long BootGdtTable \r
+\r
+ProtectedModeEntryLinearAddress:\r
+ProtectedModeEntryLinearOffset:\r
+ .long ProtectedModeEntryPoint\r
+ .word LINEAR_CODE_SEL\r
--- /dev/null
+;; @file\r
+; SEC CAR function\r
+;\r
+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;;\r
+\r
+;\r
+; Define assembler characteristics\r
+;\r
+.586p\r
+.xmm\r
+.model flat, c\r
+\r
+RET_ESI MACRO\r
+\r
+ movd esi, mm7 ; move ReturnAddress from MM7 to ESI\r
+ jmp esi\r
+\r
+ENDM\r
+\r
+.code \r
+\r
+;-----------------------------------------------------------------------------\r
+;\r
+; Section: SecCarInit\r
+;\r
+; Description: This function initializes the Cache for Data, Stack, and Code\r
+;\r
+;-----------------------------------------------------------------------------\r
+SecCarInit PROC NEAR PUBLIC\r
+\r
+ ;\r
+ ; Set up CAR\r
+ ;\r
+\r
+ xor eax, eax\r
+\r
+SecCarInitExit:\r
+\r
+ RET_ESI\r
+\r
+SecCarInit ENDP\r
+\r
+END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Abstract:\r
+#\r
+# SEC CAR function\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#-----------------------------------------------------------------------------\r
+#\r
+# Section: SecCarInit\r
+#\r
+# Description: This function initializes the Cache for Data, Stack, and Code\r
+#\r
+#-----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(SecCarInit)\r
+ASM_PFX(SecCarInit):\r
+\r
+ #\r
+ # Set up CAR\r
+ #\r
+\r
+ xor %eax, %eax\r
+\r
+SecCarInitExit:\r
+\r
+ movd %mm7, %esi #RET_ESI\r
+ jmp *%esi\r
--- /dev/null
+/** @file\r
+ Null instance of Platform Sec Lib.\r
+\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+\r
--- /dev/null
+## @file\r
+# NULL instance of Platform Sec Lib.\r
+#\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseFspSecPlatformLibNull\r
+ FILE_GUID = 03DA99B3-DDF4-4c7e-8CCA-216FC3F1F311\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = FspSecPlatformLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+ PlatformSecLibNull.c\r
+\r
+[Sources.IA32]\r
+ Ia32/Flat32.asm\r
+ Ia32/Flat32.s\r
+ Ia32/SecCarInit.asm\r
+ Ia32/SecCarInit.s\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+++ /dev/null
-/** @file\r
- Null instance of Platform Sec Lib.\r
-\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiPei.h>\r
-\r
-/**\r
- This function provides dummy function so that SecCore can pass build\r
- validation in IntelFspPkg. All real platform library instances needs\r
- to implement the real entry point in assembly.\r
-**/\r
-VOID\r
-EFIAPI\r
-_ModuleEntryPoint (\r
- VOID\r
- )\r
-{\r
- return;\r
-}\r
+++ /dev/null
-## @file\r
-# NULL instance of Platform Sec Lib.\r
-#\r
-# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = SecPlatformSecLibNull\r
- FILE_GUID = 03DA99B3-DDF4-4c7e-8CCA-216FC3F1F311\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = NULL\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IA32 X64\r
-#\r
-\r
-################################################################################\r
-#\r
-# Sources Section - list of files that are required for the build to succeed.\r
-#\r
-################################################################################\r
-\r
-[Sources]\r
- PlatformSecLibNull.c\r
-\r
-\r
-################################################################################\r
-#\r
-# Package Dependency Section - list of Package files that are required for\r
-# this module.\r
-#\r
-################################################################################\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
## @ PatchFv.py\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials are licensed and made available under\r
# the terms and conditions of the BSD License that accompanies this distribution.\r
# The full text of the license may be found at\r
offval = fsize - (0xFFFFFFFF - offval + 1)\r
fd.seek(offval)\r
bytearray = [ord(b) for b in fd.read(len)]\r
- value = 0;\r
- idx = len - 1;\r
+ value = 0\r
+ idx = len - 1\r
while idx >= 0:\r
value = value << 8 | bytearray[idx]\r
idx = idx - 1\r
fd.close()\r
return value\r
\r
+def IsFspHeaderValid (binfile):\r
+ fd = open (binfile, "rb")\r
+ bindat = fd.read(0x200)\r
+ fd.close()\r
+ HeaderList = ['FSPH' , 'FSPP' , 'FSPE']\r
+ OffsetList = []\r
+ for each in HeaderList:\r
+ if each in bindat:\r
+ idx = bindat.index(each)\r
+ else:\r
+ idx = 0\r
+ OffsetList.append(idx)\r
+ if not OffsetList[0] or not OffsetList[1]:\r
+ return False\r
+ Revision = ord(bindat[OffsetList[0] + 0x0B])\r
+ if Revision > 1 and not OffsetList[2]:\r
+ return False\r
+ return True\r
+\r
def patchDataInFile (binfile, offset, value, len=1):\r
fd = open(binfile, "r+b")\r
fsize = os.path.getsize(binfile)\r
if (offval & 0x80000000):\r
offval = fsize - (0xFFFFFFFF - offval + 1)\r
bytearray = []\r
- idx = 0;\r
+ idx = 0\r
while idx < len:\r
bytearray.append(value & 0xFF)\r
value = value >> 8\r
fd.seek(offval)\r
fd.write("".join(chr(b) for b in bytearray))\r
fd.close()\r
- return len;\r
+ return len\r
\r
\r
class Symbols:\r
values.append(self.parseBrace())\r
else:\r
break\r
- value = 1;\r
+ value = 1\r
for each in values:\r
value *= each\r
return value\r
def parseAndOr(self):\r
values = [self.parseMul()]\r
op = None\r
- value = 0xFFFFFFFF;\r
+ value = 0xFFFFFFFF\r
while True:\r
self.skipSpace()\r
char = self.getCurr()\r
fdSize = symTables.getFdSize()\r
\r
try:\r
+ ret = IsFspHeaderValid(fdFile)\r
+ if ret == False:\r
+ raise Exception ("The FSP header is not valid. Stop patching FD.")\r
comment = ""\r
for fvFile in sys.argv[3:]:\r
items = fvFile.split(",")\r
projects / mirror_edk2.git / commitdiff