Add Microcode, and Change Flash size from 3M to 4M.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18780
6f19259b-4bc3-4df7-8a09-
765794883524
18 files changed:
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r
\r
This program and the accompanying materials are licensed and made available under\r
\r
\r
This program and the accompanying materials are licensed and made available under\r
-Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r\r
This program and the accompanying materials are licensed and made available under\r\r
the terms and conditions of the BSD License that accompanies this distribution. \r\r
\r\r
This program and the accompanying materials are licensed and made available under\r\r
the terms and conditions of the BSD License that accompanies this distribution. \r\r
//00000000 007FFFFF 00800000 Flash Image\r
//\r
//00000000 00000FFF 00001000 Descriptor Region\r
//00000000 007FFFFF 00800000 Flash Image\r
//\r
//00000000 00000FFF 00001000 Descriptor Region\r
-//00001000 004FFFFF 004FF000 TXE Region\r
-//00500000 007FFFFF 00300000 BIOS Region\r
+//00001000 003FFFFF 003FF000 TXE Region\r
+//00500000 007FFFFF 00400000 BIOS Region\r
//\r
FV_REGION_INFO mRegionInfo[] = {\r
{FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},\r
//\r
FV_REGION_INFO mRegionInfo[] = {\r
{FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},\r
BUILD_TYPE = D\r
\r
BOARD_ID = BLAKCRB\r
BUILD_TYPE = D\r
\r
BOARD_ID = BLAKCRB\r
BUILD_TYPE = R\r
\r
BOARD_ID = BLAKCRB\r
BUILD_TYPE = R\r
\r
BOARD_ID = BLAKCRB\r
OEM_ID = X64\r
BUILD_TYPE = D\r
\r
OEM_ID = X64\r
BUILD_TYPE = D\r
\r
VERSION_MINOR = 01\r
BOARD_ID = BBAYCRB \r
VERSION_MINOR = 01\r
BOARD_ID = BBAYCRB \r
OEM_ID = X64\r
BUILD_TYPE = R\r
\r
OEM_ID = X64\r
BUILD_TYPE = R\r
\r
VERSION_MINOR = 01\r
BOARD_ID = BBAYCRB \r
VERSION_MINOR = 01\r
BOARD_ID = BBAYCRB \r
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
This program and the accompanying materials are licensed and made available under
# Platform Package\r
#\r
# This package provides platform specific modules.\r
# Platform Package\r
#\r
# This package provides platform specific modules.\r
-# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
# \r\r
# This program and the accompanying materials are licensed and made available under\r\r
# the terms and conditions of the BSD License that accompanies this distribution. \r\r
# \r\r
# This program and the accompanying materials are licensed and made available under\r\r
# the terms and conditions of the BSD License that accompanies this distribution. \r\r
gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003\r
gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004\r
gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009\r
gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003\r
gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004\r
gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009\r
- gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x004FF000|UINT32|0x4000000A\r
- gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFD00000|UINT32|0x4000000B\r
- gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00300000|UINT32|0x4000000C\r
+ gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x003FF000|UINT32|0x4000000A\r
+ gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFC00000|UINT32|0x4000000B\r
+ gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00400000|UINT32|0x4000000C\r
\r
[PcdsFeatureFlag]\r
## This PCD specifies whether StatusCode is reported via ISA Serial port.\r
\r
[PcdsFeatureFlag]\r
## This PCD specifies whether StatusCode is reported via ISA Serial port.\r
-DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3Mb FLASH Device.
-DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3Mb FLASH Device.
+DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device.
+DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device.
DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
DEFINE FLASH_AREA_SIZE = 0x00800000
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
DEFINE FLASH_AREA_SIZE = 0x00800000
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
-DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00030000
-DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFD00000
+DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
+DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
-DEFINE FLASH_REGION_VPD_OFFSET = 0x00030000
+DEFINE FLASH_REGION_VPD_OFFSET = 0x00130000
DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0016E000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00070000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00170000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
!if $(MINNOW2_FSP_BUILD) == TRUE
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
!if $(MINNOW2_FSP_BUILD) == TRUE
-DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000B0000
+DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x001B0000
DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
-DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x000F8000
+DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x001F8000
DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
!endif
DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
!endif
-DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00100000
+DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00200000
DEFINE FLASH_REGION_FVMAIN_SIZE = 0x001A5000
DEFINE FLASH_REGION_FVMAIN_SIZE = 0x001A5000
-DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x002A5000
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x003A5000
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002B000
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002B000
-DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x002D0000
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x003D0000
DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00030000
################################################################################
DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00030000
################################################################################
-DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3Mb FLASH Device.
-DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3Mb FLASH Device.
-DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3Mb FLASH Device.
+DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device.
+DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device.
DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
DEFINE FLASH_AREA_SIZE = 0x00800000
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
DEFINE FLASH_AREA_SIZE = 0x00800000
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
-DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00030000
-DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFD00000
+DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
+DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
-DEFINE FLASH_REGION_VPD_OFFSET = 0x00030000
+DEFINE FLASH_REGION_VPD_OFFSET = 0x00130000
DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0016E000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
-DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00070000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00170000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
!if $(MINNOW2_FSP_BUILD) == TRUE
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
!if $(MINNOW2_FSP_BUILD) == TRUE
-DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000B0000
+DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x001B0000
DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
-DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x000F8000
+DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x001F8000
DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
!endif
DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
!endif
-DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00100000
+DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00200000
DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00196000
DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00196000
-
-DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00296000
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00396000
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002C000
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002C000
-
-DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x002C2000
+
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x003C2000
DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x0003E000
################################################################################
DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x0003E000
################################################################################
[PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE)
[PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE)
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
# $(FLASH_REGION_VLVMICROCODE_SIZE)
# $(FLASH_REGION_VLVMICROCODE_SIZE)
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
[PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE)
[PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE)
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
# $(FLASH_REGION_VLVMICROCODE_SIZE)
# $(FLASH_REGION_VLVMICROCODE_SIZE)
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
[PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE)
[PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE)
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
# $(FLASH_REGION_VLVMICROCODE_SIZE)
# $(FLASH_REGION_VLVMICROCODE_SIZE)
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
-// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r
// \r\r
// This program and the accompanying materials are licensed and made available under\r\r
// the terms and conditions of the BSD License that accompanies this distribution. \r\r
// \r\r
// This program and the accompanying materials are licensed and made available under\r\r
// the terms and conditions of the BSD License that accompanies this distribution. \r\r
#\r
\r
HEADER=IFWI_HEADER\r
#\r
\r
HEADER=IFWI_HEADER\r
-SEC_VERSION=1.0.2.1067\r
+SEC_VERSION=1.0.2.1060v5\r
BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM
BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin
cp -f $BUILD_PATH/FV/VLV.fd $WORKSPACE/$BIOS_Name
BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM
BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin
cp -f $BUILD_PATH/FV/VLV.fd $WORKSPACE/$BIOS_Name
+SEC_VERSION=1.0.2.1060v5
cat $IFWI_HEADER_FILE ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID
cat $IFWI_HEADER_FILE ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID