Add EnableCache() and DisableCache() implementations for IA32 and X64 to the BaseLib

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6705 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index ff09e05a684b13c32969989d96c827cd774c3fc0..7eedb2a35f69f29763d11f3d98945e25c4a18145 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -157,6 +157,8 @@
   Ia32/ARShiftU64.c | MSFT \r
   Ia32/Thunk16.asm | MSFT\r
   Ia32/EnablePaging64.asm | MSFT\r
+  Ia32/EnableCache.c | MSFT\r
+  Ia32/DisableCache.c | MSFT\r
   SynchronizationMsc.c  | MSFT\r
 \r
   Ia32/Wbinvd.asm | INTEL \r
@@ -253,6 +255,8 @@
   Ia32/ARShiftU64.asm | INTEL \r
   Ia32/Thunk16.asm | INTEL\r
   Ia32/EnablePaging64.asm | INTEL\r
+  Ia32/EnableCache.asm | INTEL\r
+  Ia32/DisableCache.asm | INTEL\r
   Synchronization.c | INTEL\r
 \r
   Ia32/Thunk16.S | GCC \r
@@ -349,6 +353,8 @@
   Ia32/ARShiftU64.S | GCC \r
   Ia32/RShiftU64.S | GCC \r
   Ia32/LShiftU64.S | GCC \r
+  Ia32/EnableCache.S | GCC\r
+  Ia32/DisableCache.S | GCC\r
   SynchronizationGcc.c  | GCC\r
 \r
   Ia32/DivS64x64Remainder.c\r
@@ -448,6 +454,8 @@
   X64/SwitchStack.asm\r
   X64/InterlockedCompareExchange64.asm \r
   X64/InterlockedCompareExchange32.asm \r
+  X64/EnableCache.asm\r
+  X64/DisableCache.asm\r
 \r
   X64/InterlockedDecrement.c | MSFT \r
   X64/InterlockedIncrement.c | MSFT \r
@@ -563,6 +571,8 @@
   X64/CpuIdEx.S | GCC \r
   X64/CpuBreakpoint.S | GCC \r
   SynchronizationGcc.c  | GCC \r
+  X64/EnableCache.S | GCC\r
+  X64/DisableCache.S | GCC\r
   ChkStkGcc.c  | GCC \r
 \r
 [Sources.IPF]\r

diff --git a/MdePkg/Library/BaseLib/Ia32/DisableCache.S b/MdePkg/Library/BaseLib/Ia32/DisableCache.S
new file mode 100644 (file)
index 0000000..b11245e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/DisableCache.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#   DisableCache.S\r
+#\r
+# Abstract:\r
+#\r
+#   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+#   WBINVD instruction.\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmDisableCache (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+.globl ASM_PFX(AsmDisableCache)\r
+ASM_PFX(AsmDisableCache):\r
+    movl    %cr0, %eax\r
+    btsl    $30, %eax\r
+    btrl    $29, %eax\r
+    movl    %eax, %cr0\r
+    wbinvd\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/Ia32/DisableCache.asm b/MdePkg/Library/BaseLib/Ia32/DisableCache.asm
new file mode 100644 (file)
index 0000000..0d92472
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/DisableCache.asm
@@ -0,0 +1,45 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   DisableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+;   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+;   WBINVD instruction.\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    .386p\r
+    .model  flat,C\r
+    .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmDisableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+AsmDisableCache PROC\r
+    mov     eax, cr0\r
+    bts     eax, 30\r
+    btr     eax, 29\r
+    mov     cr0, eax\r
+    wbinvd\r
+    ret\r
+AsmDisableCache ENDP\r
+\r
+    END\r

diff --git a/MdePkg/Library/BaseLib/Ia32/DisableCache.c b/MdePkg/Library/BaseLib/Ia32/DisableCache.c
new file mode 100644 (file)
index 0000000..d2d028a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/DisableCache.c
@@ -0,0 +1,36 @@
+/** @file\r
+  AsmDisableCache function\r
+\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+/**\r
+  Disables caches.\r
+\r
+  Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+  WBINVD instruction.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmDisableCache (\r
+  VOID\r
+  )\r
+{\r
+  _asm {\r
+    mov     eax, cr0\r
+    bts     eax, 30\r
+    btr     eax, 29\r
+    mov     cr0, eax\r
+    wbinvd\r
+  }\r
+}\r
+\r

diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.S b/MdePkg/Library/BaseLib/Ia32/EnableCache.S
new file mode 100644 (file)
index 0000000..bdb4bdb
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#   EnableCache.S\r
+#\r
+# Abstract:\r
+#\r
+#   Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+#   the NW bit of CR0 to 0\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmEnableCache (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+.globl ASM_PFX(AsmEnableCache)\r
+ASM_PFX(AsmEnableCache):\r
+    wbinvd\r
+    movl    %cr0, %eax\r
+    btrl    $30, %eax\r
+    btrl    $29, %eax\r
+    movl    %eax, %cr0\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.asm b/MdePkg/Library/BaseLib/Ia32/EnableCache.asm
new file mode 100644 (file)
index 0000000..e25a5bf
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.asm
@@ -0,0 +1,45 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   EnableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+;  the NW bit of CR0 to 0\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    .386p\r
+    .model  flat,C\r
+    .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmEnableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+AsmEnableCache PROC\r
+    wbinvd\r
+    mov     eax, cr0\r
+    btr     eax, 29\r
+    btr     eax, 30\r
+    mov     cr0, eax\r
+    ret\r
+AsmEnableCache ENDP\r
+\r
+    END\r

diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.c b/MdePkg/Library/BaseLib/Ia32/EnableCache.c
new file mode 100644 (file)
index 0000000..59e2b43
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.c
@@ -0,0 +1,36 @@
+/** @file\r
+  AsmEnableCache function\r
+\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+/**\r
+  Enabled caches.\r
+\r
+  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+  the NW bit of CR0 to 0\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmEnableCache (\r
+  VOID\r
+  )\r
+{\r
+  _asm {\r
+    wbinvd\r
+    mov     eax, cr0\r
+    btr     eax, 30\r
+    btr     eax, 29\r
+    mov     cr0, eax\r
+  }\r
+}\r
+\r

diff --git a/MdePkg/Library/BaseLib/X64/DisableCache.S b/MdePkg/Library/BaseLib/X64/DisableCache.S
new file mode 100644 (file)
index 0000000..44f82bb
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/DisableCache.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#   DisableCache.S\r
+#\r
+# Abstract:\r
+#\r
+#   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+#   WBINVD instruction.\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmDisableCache (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+.globl ASM_PFX(AsmDisableCache)\r
+ASM_PFX(AsmDisableCache):\r
+    movl    %cr0, %rax\r
+    btsl    $30, %rax\r
+    btrl    $29, %rax\r
+    movl    %rax, %cr0\r
+    wbinvd\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/X64/DisableCache.asm b/MdePkg/Library/BaseLib/X64/DisableCache.asm
new file mode 100644 (file)
index 0000000..5ad85c7
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/DisableCache.asm
@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   DisableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+;   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+;   WBINVD instruction.\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmDisableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+AsmDisableCache PROC\r
+    mov     rax, cr0\r
+    bts     rax, 30\r
+    btr     rax, 29\r
+    mov     cr0, rax\r
+    wbinvd\r
+    ret\r
+AsmDisableCache ENDP\r
+\r
+    END\r

diff --git a/MdePkg/Library/BaseLib/X64/EnableCache.S b/MdePkg/Library/BaseLib/X64/EnableCache.S
new file mode 100644 (file)
index 0000000..99257d6
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/EnableCache.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#   EnableCache.S\r
+#\r
+# Abstract:\r
+#\r
+#   Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+#   the NW bit of CR0 to 0\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmEnableCache (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+.globl ASM_PFX(AsmEnableCache)\r
+ASM_PFX(AsmEnableCache):\r
+    wbinvd\r
+    movl    %cr0, %rax\r
+    btrl    $30, %rax\r
+    btrl    $29, %rax\r
+    movl    %rax, %cr0\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/X64/EnableCache.asm b/MdePkg/Library/BaseLib/X64/EnableCache.asm
new file mode 100644 (file)
index 0000000..5846cf0
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/EnableCache.asm
@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   EnableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+;  the NW bit of CR0 to 0\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmEnableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+AsmEnableCache PROC\r
+    wbinvd\r
+    mov     rax, cr0\r
+    btr     rax, 29\r
+    btr     rax, 30\r
+    mov     cr0, rax\r
+    ret\r
+AsmEnableCache ENDP\r
+\r
+    END\r