OvmfPkg: Make an Ia32/X64 hybrid build work with SEV

The BaseMemEncryptSevLib functionality was updated to rely on the use of
the OVMF/SEV workarea to check for SEV guests. However, this area is only
updated when running the X64 OVMF build, not the hybrid Ia32/X64 build.
Base SEV support is allowed under the Ia32/X64 build, but it now fails
to boot as a result of the change.

Update the ResetVector code to check for SEV features when built for
32-bit mode, not just 64-bit mode (requiring updates to both the Ia32
and Ia32X64 fdf files).

Fixes: f1d1c337e7c0575da7fd248b2dd9cffc755940df
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Michael Roth <michael.roth@amd.com>
Cc: Min Xu <min.m.xu@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf
index 3ab1755749d4059def65afc1291ed236e838955d..57d13b7130bc6b90e653e848cd82120f14d66a47 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32.fdf
+++ b/OvmfPkg/OvmfPkgIa32.fdf
@@ -76,6 +76,9 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|gUefiOvmfPkgTokenSpaceGuid.
 0x007000|0x001000\r
 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize\r
 \r
+0x008000|0x001000\r
+gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize\r
+\r
 0x010000|0x010000\r
 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize\r
 \r
@@ -87,6 +90,14 @@ FV = PEIFV
 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize\r
 FV = DXEFV\r
 \r
+##########################################################################################\r
+# Set the SEV-ES specific work area PCDs (used for all forms of SEV since the\r
+# the SEV STATUS MSR is now saved in the work area)\r
+#\r
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase = $(MEMFD_BASE_ADDRESS) +  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader\r
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader\r
+##########################################################################################\r
+\r
 ################################################################################\r
 \r
 [FV.SECFV]\r

diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf
index e1638fa6ea3857d1f8707935c7fb9d28c67bc28b..ccde366887a907e06a320c69c88071109e8a247e 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32X64.fdf
+++ b/OvmfPkg/OvmfPkgIa32X64.fdf
@@ -90,6 +90,14 @@ FV = PEIFV
 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize\r
 FV = DXEFV\r
 \r
+##########################################################################################\r
+# Set the SEV-ES specific work area PCDs (used for all forms of SEV since the\r
+# the SEV STATUS MSR is now saved in the work area)\r
+#\r
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase = $(MEMFD_BASE_ADDRESS) +  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader\r
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader\r
+##########################################################################################\r
+\r
 ################################################################################\r
 \r
 [FV.SECFV]\r

diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf
index aa9a83032d9bd8ca0965a43a02219c803327ecb1..438806fba8f1acb30f8698171636e68785ec338f 100644 (file)
--- a/OvmfPkg/OvmfPkgX64.fdf
+++ b/OvmfPkg/OvmfPkgX64.fdf
@@ -106,7 +106,8 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvm
 FV = DXEFV\r
 \r
 ##########################################################################################\r
-# Set the SEV-ES specific work area PCDs\r
+# Set the SEV-ES specific work area PCDs (used for all forms of SEV since the\r
+# the SEV STATUS MSR is now saved in the work area)\r
 #\r
 SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase = $(MEMFD_BASE_ADDRESS) +  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader\r
 SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader\r

diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
index 864d68385342c7d49bb41154b4c0b8c2038a479b..9350b04068332e2f888c8ad82caf08d9cfa88653 100644 (file)
--- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm
+++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
@@ -150,6 +150,8 @@ BITS    32
 SevEsUnexpectedRespTerminate:\r
     TerminateVmgExit    TERM_UNEXPECTED_RESP_CODE\r
 \r
+%ifdef ARCH_X64\r
+\r
 ; If SEV-ES is enabled then initialize and make the GHCB page shared\r
 SevClearPageEncMaskForGhcbPage:\r
     ; Check if SEV is enabled\r
@@ -209,6 +211,8 @@ GetSevCBitMaskAbove31:
 GetSevCBitMaskAbove31Exit:\r
     OneTimeCallRet GetSevCBitMaskAbove31\r
 \r
+%endif\r
+\r
 ; Check if Secure Encrypted Virtualization (SEV) features are enabled.\r
 ;\r
 ; Register usage is tight in this routine, so multiple calls for the\r

diff --git a/OvmfPkg/ResetVector/Main.asm b/OvmfPkg/ResetVector/Main.asm
index 5cfc0b5c72b11982c2eaf3c6b05a9fc9421bb10d..46cfa87c4c0a248d3bc6af11c17c4e071cb5a31c 100644 (file)
--- a/OvmfPkg/ResetVector/Main.asm
+++ b/OvmfPkg/ResetVector/Main.asm
@@ -75,6 +75,12 @@ SearchBfv:
 \r
 %ifdef ARCH_IA32\r
 \r
+    ;\r
+    ; SEV support can be built and run using the Ia32/X64 split environment.\r
+    ; Set the OVMF/SEV work area as appropriate.\r
+    ;\r
+    OneTimeCall CheckSevFeatures\r
+\r
     ;\r
     ; Restore initial EAX value into the EAX register\r
     ;\r

diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb
index 9421f48189074ee0957a6a9888c772fa9173a3f4..94fbb0a87b37eec03e3f7403fb908b1fc57058b4 100644 (file)
--- a/OvmfPkg/ResetVector/ResetVector.nasmb
+++ b/OvmfPkg/ResetVector/ResetVector.nasmb
@@ -47,7 +47,36 @@
 %include "Ia32/SearchForBfvBase.asm"\r
 %include "Ia32/SearchForSecEntry.asm"\r
 \r
-%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))\r
+%define WORK_AREA_GUEST_TYPE          (FixedPcdGet32 (PcdOvmfWorkAreaBase))\r
+%define PT_ADDR(Offset)               (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))\r
+\r
+%define GHCB_PT_ADDR                  (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))\r
+%define GHCB_BASE                     (FixedPcdGet32 (PcdOvmfSecGhcbBase))\r
+%define GHCB_SIZE                     (FixedPcdGet32 (PcdOvmfSecGhcbSize))\r
+%define SEV_ES_WORK_AREA              (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
+%define SEV_ES_WORK_AREA_SIZE         25\r
+%define SEV_ES_WORK_AREA_STATUS_MSR   (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
+%define SEV_ES_WORK_AREA_RDRAND       (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)\r
+%define SEV_ES_WORK_AREA_ENC_MASK     (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)\r
+%define SEV_ES_WORK_AREA_RECEIVED_VC  (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 24)\r
+%define SEV_ES_VC_TOP_OF_STACK        (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))\r
+%define SEV_SNP_SECRETS_BASE          (FixedPcdGet32 (PcdOvmfSnpSecretsBase))\r
+%define SEV_SNP_SECRETS_SIZE          (FixedPcdGet32 (PcdOvmfSnpSecretsSize))\r
+%define CPUID_BASE                    (FixedPcdGet32 (PcdOvmfCpuidBase))\r
+%define CPUID_SIZE                    (FixedPcdGet32 (PcdOvmfCpuidSize))\r
+%define SNP_SEC_MEM_BASE_DESC_1       (FixedPcdGet32 (PcdOvmfSecPageTablesBase))\r
+%define SNP_SEC_MEM_SIZE_DESC_1       (FixedPcdGet32 (PcdOvmfSecGhcbBase) - SNP_SEC_MEM_BASE_DESC_1)\r
+;\r
+; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used\r
+; as GHCB shared page and second is used for bookkeeping to support the\r
+; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM\r
+; does not need to validate the shared page but it need to validate the\r
+; bookkeeping page.\r
+;\r
+%define SNP_SEC_MEM_BASE_DESC_2       (GHCB_BASE + 0x1000)\r
+%define SNP_SEC_MEM_SIZE_DESC_2       (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_BASE_DESC_2)\r
+%define SNP_SEC_MEM_BASE_DESC_3       (CPUID_BASE + CPUID_SIZE)\r
+%define SNP_SEC_MEM_SIZE_DESC_3       (FixedPcdGet32 (PcdOvmfPeiMemFvBase) - SNP_SEC_MEM_BASE_DESC_3)\r
 \r
 %ifdef ARCH_X64\r
   #include <AutoGen.h>\r
@@ -94,44 +123,15 @@
   %define TDX_WORK_AREA_PGTBL_READY (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 4)\r
   %define TDX_WORK_AREA_GPAW        (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 8)\r
 \r
-  %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))\r
-\r
-  %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))\r
-  %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))\r
-  %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))\r
-  %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
-  %define SEV_ES_WORK_AREA_SIZE 25\r
-  %define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
-  %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)\r
-  %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)\r
-  %define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 24)\r
-  %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))\r
-  %define SEV_SNP_SECRETS_BASE  (FixedPcdGet32 (PcdOvmfSnpSecretsBase))\r
-  %define SEV_SNP_SECRETS_SIZE  (FixedPcdGet32 (PcdOvmfSnpSecretsSize))\r
-  %define CPUID_BASE  (FixedPcdGet32 (PcdOvmfCpuidBase))\r
-  %define CPUID_SIZE  (FixedPcdGet32 (PcdOvmfCpuidSize))\r
-  %define SNP_SEC_MEM_BASE_DESC_1 (FixedPcdGet32 (PcdOvmfSecPageTablesBase))\r
-  %define SNP_SEC_MEM_SIZE_DESC_1 (FixedPcdGet32 (PcdOvmfSecGhcbBase) - SNP_SEC_MEM_BASE_DESC_1)\r
-  ;\r
-  ; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used\r
-  ; as GHCB shared page and second is used for bookkeeping to support the\r
-  ; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM\r
-  ; does not need to validate the shared page but it need to validate the\r
-  ; bookkeeping page.\r
-  ;\r
-  %define SNP_SEC_MEM_BASE_DESC_2 (GHCB_BASE + 0x1000)\r
-  %define SNP_SEC_MEM_SIZE_DESC_2 (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_BASE_DESC_2)\r
-  %define SNP_SEC_MEM_BASE_DESC_3 (CPUID_BASE + CPUID_SIZE)\r
-  %define SNP_SEC_MEM_SIZE_DESC_3 (FixedPcdGet32 (PcdOvmfPeiMemFvBase) - SNP_SEC_MEM_BASE_DESC_3)\r
-\r
-%include "X64/IntelTdxMetadata.asm"\r
-%include "Ia32/Flat32ToFlat64.asm"\r
-%include "Ia32/AmdSev.asm"\r
-%include "Ia32/PageTables64.asm"\r
-%include "Ia32/IntelTdx.asm"\r
-%include "X64/OvmfSevMetadata.asm"\r
+  %include "X64/IntelTdxMetadata.asm"\r
+  %include "Ia32/Flat32ToFlat64.asm"\r
+  %include "Ia32/PageTables64.asm"\r
+  %include "Ia32/IntelTdx.asm"\r
+  %include "X64/OvmfSevMetadata.asm"\r
 %endif\r
 \r
+%include "Ia32/AmdSev.asm"\r
+\r
 %include "Ia16/Real16ToFlat32.asm"\r
 %include "Ia16/Init16.asm"\r
 \r