IntelFsp2Pkg: FSPM_ARCH2_UPD mismatching bug.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019

FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and
should be fixed for both IA32 and X64 builds.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 5dada2af54a4412d0d4cbb089546327b63635ee4..61ab4612a3b92d5493554789c28085d634e95b6d 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -40,12 +40,13 @@ struc FSPM_UPD_COMMON_FSP24
     .Revision:                  resb  1\r
     .Reserved:                  resb  3\r
     .Length                     resd  1\r
+    .NvsBufferPtr               resq  1\r
     .StackBase:                 resq  1\r
     .StackSize:                 resq  1\r
     .BootLoaderTolumSize:       resd  1\r
     .BootMode:                  resd  1\r
     .FspEventHandler            resq  1\r
-    .Reserved1:                 resb 24\r
+    .Reserved1:                 resb 16\r
     ; }\r
     .size:\r
 endstruc\r

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
index dacf5158452ce8ffdd451233a3f38c453f4b04d1..2d2f75b1f049b5a8dd75ea303c404b46921e0edc 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
@@ -22,12 +22,13 @@ struc FSPM_UPD_COMMON_FSP24
     .Revision:                  resb  1\r
     .Reserved:                  resb  3\r
     .Length                     resd  1\r
+    .NvsBufferPtr               resq  1\r
     .StackBase:                 resq  1\r
     .StackSize:                 resq  1\r
     .BootLoaderTolumSize:       resd  1\r
     .BootMode:                  resd  1\r
     .FspEventHandler            resq  1\r
-    .Reserved1:                 resb 24\r
+    .Reserved1:                 resb 16\r
     ; }\r
     .size:\r
 endstruc\r