--- /dev/null
+/** @file\r
+ Intel FSP API definition from Intel Firmware Support Package External\r
+ Architecture Specification, April 2014, revision 001.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FSP_API_H_\r
+#define _FSP_API_H_\r
+\r
+typedef UINT32 FSP_STATUS;\r
+#define FSPAPI EFIAPI\r
+\r
+/**\r
+ FSP Init continuation function prototype.\r
+ Control will be returned to this callback function after FspInit API call.\r
+\r
+ @param[in] Status Status of the FSP INIT API.\r
+ @param[in] HobBufferPtr Pointer to the HOB data structure defined in the PI specification.\r
+**/\r
+typedef\r
+VOID\r
+(* CONTINUATION_PROC) (\r
+ IN FSP_STATUS Status,\r
+ IN VOID *HobListPtr\r
+ );\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ ///\r
+ /// Base address of the microcode region.\r
+ ///\r
+ UINT32 MicrocodeRegionBase;\r
+ ///\r
+ /// Length of the microcode region.\r
+ ///\r
+ UINT32 MicrocodeRegionLength;\r
+ ///\r
+ /// Base address of the cacheable flash region.\r
+ ///\r
+ UINT32 CodeRegionBase;\r
+ ///\r
+ /// Length of the cacheable flash region.\r
+ ///\r
+ UINT32 CodeRegionLength;\r
+} FSP_TEMP_RAM_INIT_PARAMS;\r
+\r
+typedef struct {\r
+ ///\r
+ /// Non-volatile storage buffer pointer.\r
+ ///\r
+ VOID *NvsBufferPtr;\r
+ ///\r
+ /// Runtime buffer pointer\r
+ ///\r
+ VOID *RtBufferPtr;\r
+ ///\r
+ /// Continuation function address\r
+ ///\r
+ CONTINUATION_PROC ContinuationFunc;\r
+} FSP_INIT_PARAMS;\r
+\r
+typedef struct {\r
+ ///\r
+ /// Stack top pointer used by the bootloader.\r
+ /// The new stack frame will be set up at this location after FspInit API call.\r
+ ///\r
+ UINT32 *StackTop;\r
+ ///\r
+ /// Current system boot mode.\r
+ ///\r
+ UINT32 BootMode;\r
+ ///\r
+ /// User platform configuraiton data region pointer.\r
+ ///\r
+ VOID *UpdDataRgnPtr;\r
+ ///\r
+ /// Reserved\r
+ ///\r
+ UINT32 Reserved[7];\r
+} FSP_INIT_RT_COMMON_BUFFER;\r
+\r
+typedef enum {\r
+ ///\r
+ /// Notification code for post PCI enuermation\r
+ ///\r
+ EnumInitPhaseAfterPciEnumeration = 0x20,\r
+ ///\r
+ /// Notification code before transfering control to the payload\r
+ ///\r
+ EnumInitPhaseReadyToBoot = 0x40\r
+} FSP_INIT_PHASE;\r
+\r
+typedef struct {\r
+ ///\r
+ /// Notification phase used for NotifyPhase API\r
+ ///\r
+ FSP_INIT_PHASE Phase;\r
+} NOTIFY_PHASE_PARAMS;\r
+\r
+#pragma pack()\r
+\r
+/**\r
+ This FSP API is called soon after coming out of reset and before memory and stack is\r
+ available. This FSP API will load the microcode update, enable code caching for the\r
+ region specified by the boot loader and also setup a temporary stack to be used until\r
+ main memory is initialized.\r
+\r
+ A hardcoded stack can be set up with the following values, and the "esp" register\r
+ initialized to point to this hardcoded stack.\r
+ 1. The return address where the FSP will return control after setting up a temporary\r
+ stack.\r
+ 2. A pointer to the input parameter structure\r
+\r
+ However, since the stack is in ROM and not writeable, this FSP API cannot be called\r
+ using the "call" instruction, but needs to be jumped to.\r
+\r
+ @param[in] TempRaminitParamPtr Address pointer to the FSP_TEMP_RAM_INIT_PARAMS structure.\r
+\r
+ @retval FSP_SUCCESS Temp RAM was initialized successfully.\r
+ @retval FSP_INVALID_PARAMETER Input parameters are invalid..\r
+ @retval FSP_NOT_FOUND No valid microcode was found in the microcode region.\r
+ @retval FSP_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval FSP_DEVICE_ERROR Temp RAM initialization failed.\r
+\r
+ If this function is successful, the FSP initializes the ECX and EDX registers to point to\r
+ a temporary but writeable memory range available to the boot loader and returns with\r
+ FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r
+ memory range and EDX points to the end of the range. Boot loader is free to use the\r
+ whole range described. Typically the boot loader can reload the ESP register to point\r
+ to the end of this returned range so that it can be used as a standard stack.\r
+**/\r
+typedef\r
+FSP_STATUS\r
+(FSPAPI *FSP_TEMP_RAM_INIT) (\r
+ IN FSP_TEMP_RAM_INIT_PARAMS *FspTempRamInitPtr\r
+ );\r
+\r
+/**\r
+ This FSP API is called after TempRamInitEntry. This FSP API initializes the memory,\r
+ the CPU and the chipset to enable normal operation of these devices. This FSP API\r
+ accepts a pointer to a data structure that will be platform dependent and defined for\r
+ each FSP binary. This will be documented in the Integration Guide for each FSP\r
+ release.\r
+ The boot loader provides a continuation function as a parameter when calling FspInit.\r
+ After FspInit completes its execution, it does not return to the boot loader from where\r
+ it was called but instead returns control to the boot loader by calling the continuation\r
+ function which is passed to FspInit as an argument.\r
+\r
+ @param[in] FspInitParamPtr Address pointer to the FSP_INIT_PARAMS structure.\r
+\r
+ @retval FSP_SUCCESS FSP execution environment was initialized successfully.\r
+ @retval FSP_INVALID_PARAMETER Input parameters are invalid.\r
+ @retval FSP_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval FSP_DEVICE_ERROR FSP initialization failed.\r
+**/\r
+typedef\r
+FSP_STATUS\r
+(FSPAPI *FSP_FSP_INIT) (\r
+ IN OUT FSP_INIT_PARAMS *FspInitParamPtr\r
+ );\r
+\r
+/**\r
+ This FSP API is used to notify the FSP about the different phases in the boot process.\r
+ This allows the FSP to take appropriate actions as needed during different initialization\r
+ phases. The phases will be platform dependent and will be documented with the FSP\r
+ release. The current FSP supports two notify phases:\r
+ Post PCI enumeration\r
+ Ready To Boot\r
+\r
+ @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r
+\r
+ @retval FSP_SUCCESS The notification was handled successfully.\r
+ @retval FSP_UNSUPPORTED The notification was not called in the proper order.\r
+ @retval FSP_INVALID_PARAMETER The notification code is invalid.\r
+**/\r
+typedef\r
+FSP_STATUS\r
+(FSPAPI *FSP_NOTFY_PHASE) (\r
+ IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r
+ );\r
+\r
+///\r
+/// FSP API Return Status Code\r
+///\r
+#define FSP_SUCCESS 0x00000000\r
+#define FSP_INVALID_PARAMETER 0x80000002\r
+#define FSP_UNSUPPORTED 0x80000003\r
+#define FSP_NOT_READY 0x80000006\r
+#define FSP_DEVICE_ERROR 0x80000007\r
+#define FSP_OUT_OF_RESOURCES 0x80000009\r
+#define FSP_VOLUME_CORRUPTED 0x8000000A\r
+#define FSP_NOT_FOUND 0x8000000E\r
+#define FSP_TIMEOUT 0x80000012\r
+#define FSP_ABORTED 0x80000015\r
+#define FSP_INCOMPATIBLE_VERSION 0x80000010\r
+#define FSP_SECURITY_VIOLATION 0x8000001A\r
+#define FSP_CRC_ERROR 0x8000001B\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Intel FSP Info Header definition from Intel Firmware Support Package External\r
+ Architecture Specification, April 2014, revision 001.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FSP_INFO_HEADER_H_\r
+#define _FSP_INFO_HEADER_H_\r
+\r
+///\r
+/// Fixed FSP header offset in the FSP image\r
+///\r
+#define FSP_INFO_HEADER_OFF 0x94\r
+\r
+#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ ///\r
+ /// Signature ('FSPH') for the FSP Information Header\r
+ ///\r
+ UINT32 Signature;\r
+ ///\r
+ /// Length of the FSP Information Header\r
+ ///\r
+ UINT32 HeaderLength;\r
+ ///\r
+ /// Reserved\r
+ ///\r
+ UINT8 Reserved1[3];\r
+ ///\r
+ /// Revision of the FSP Information Header\r
+ ///\r
+ UINT8 HeaderRevision;\r
+ ///\r
+ /// Revision of the FSP binary\r
+ ///\r
+ UINT32 ImageRevision;\r
+\r
+\r
+ ///\r
+ /// Signature string that will help match the FSP Binary to a supported\r
+ /// hardware configuration.\r
+ ///\r
+ CHAR8 ImageId[8];\r
+ ///\r
+ /// Size of the entire FSP binary\r
+ ///\r
+ UINT32 ImageSize;\r
+ ///\r
+ /// FSP binary preferred base address\r
+ ///\r
+ UINT32 ImageBase;\r
+\r
+\r
+ ///\r
+ /// Attribute for the FSP binary\r
+ ///\r
+ UINT32 ImageAttribute;\r
+ ///\r
+ /// Offset of the FSP configuration region\r
+ ///\r
+ UINT32 CfgRegionOffset;\r
+ ///\r
+ /// Size of the FSP configuration region\r
+ ///\r
+ UINT32 CfgRegionSize;\r
+ ///\r
+ /// Number of API entries this FSP supports\r
+ ///\r
+ UINT32 ApiEntryNum;\r
+\r
+\r
+ ///\r
+ /// TempRamInit API entry offset\r
+ ///\r
+ UINT32 TempRamInitEntryOffset;\r
+ ///\r
+ /// FspInit API entry offset\r
+ ///\r
+ UINT32 FspInitEntryOffset;\r
+ ///\r
+ /// NotifyPhase API entry offset\r
+ ///\r
+ UINT32 NotifyPhaseEntryOffset;\r
+ ///\r
+ /// Reserved\r
+ ///\r
+ UINT32 Reserved2;\r
+\r
+} FSP_INFO_HEADER;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Intel FSP Header File Guid definition from Intel Firmware Support Package External\r
+ Architecture Specification, April 2014, revision 001.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __FSP_HEADER_FILE_GUID__\r
+#define __FSP_HEADER_FILE_GUID__\r
+\r
+extern EFI_GUID gFspHeaderFileGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Intel FSP Hob Guid definition from Intel Firmware Support Package External\r
+ Architecture Specification, April 2014, revision 001.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __GUID_HOB_FSP_EAS_GUID__\r
+#define __GUID_HOB_FSP_EAS_GUID__\r
+\r
+extern EFI_GUID gFspBootLoaderTemporaryMemoryGuid;\r
+extern EFI_GUID gFspReservedMemoryResourceHobGuid;\r
+extern EFI_GUID gFspNonVolatileStorageHobGuid;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+#\r
+# Provides driver and definitions to build fsp in EDKII bios.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = IntelFspPkg\r
+ PACKAGE_GUID = 444C6CDF-55BD-4744-8F74-AE98B003B955\r
+ PACKAGE_VERSION = 0.1\r
+\r
+[Includes]\r
+ Include\r
+\r
+[Guids]\r
+ # Guid define in FSP EAS\r
+ gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
+ gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
+ gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
+ gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
+\r
--- /dev/null
+/** @file\r
+ Locate the entry point for the PEI Core\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+\r
+#include "SecMain.h"\r
+\r
+/**\r
+ Find core image base.\r
+\r
+ @param[in] BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param[out] SecCoreImageBase The base address of the SEC core image.\r
+ @param[out] PeiCoreImageBase The base address of the PEI core image.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FindImageBase (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,\r
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase\r
+ )\r
+{\r
+ EFI_PHYSICAL_ADDRESS CurrentAddress;\r
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;\r
+ EFI_FFS_FILE_HEADER *File;\r
+ UINT32 Size;\r
+ EFI_PHYSICAL_ADDRESS EndOfFile;\r
+ EFI_COMMON_SECTION_HEADER *Section;\r
+ EFI_PHYSICAL_ADDRESS EndOfSection;\r
+\r
+ *SecCoreImageBase = 0;\r
+ *PeiCoreImageBase = 0;\r
+\r
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;\r
+ EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;\r
+\r
+ //\r
+ // Loop through the FFS files in the Boot Firmware Volume\r
+ //\r
+ for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {\r
+\r
+ CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;\r
+ if (CurrentAddress > EndOfFirmwareVolume) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;\r
+ if (IS_FFS_FILE2 (File)) {\r
+ Size = FFS_FILE2_SIZE (File);\r
+ if (Size <= 0x00FFFFFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ } else {\r
+ Size = FFS_FILE_SIZE (File);\r
+ if (Size < sizeof (EFI_FFS_FILE_HEADER)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ EndOfFile = CurrentAddress + Size;\r
+ if (EndOfFile > EndOfFirmwareVolume) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Look for SEC Core / PEI Core files\r
+ //\r
+ if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&\r
+ File->Type != EFI_FV_FILETYPE_PEI_CORE) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Loop through the FFS file sections within the FFS file\r
+ //\r
+ if (IS_FFS_FILE2 (File)) {\r
+ EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));\r
+ } else {\r
+ EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));\r
+ }\r
+ for (;;) {\r
+ CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;\r
+ Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;\r
+\r
+ if (IS_SECTION2 (Section)) {\r
+ Size = SECTION2_SIZE (Section);\r
+ if (Size <= 0x00FFFFFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ } else {\r
+ Size = SECTION_SIZE (Section);\r
+ if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ EndOfSection = CurrentAddress + Size;\r
+ if (EndOfSection > EndOfFile) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Look for executable sections\r
+ //\r
+ if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {\r
+ if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {\r
+ if (IS_SECTION2 (Section)) {\r
+ *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+ } else {\r
+ *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+ }\r
+ } else {\r
+ if (IS_SECTION2 (Section)) {\r
+ *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+ } else {\r
+ *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Both SEC Core and PEI Core images found\r
+ //\r
+ if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Find and return Pei Core entry point.\r
+\r
+ It also find SEC and PEI Core file debug inforamtion. It will report them if\r
+ remote debug is enabled.\r
+\r
+ @param[in] BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param[out] PeiCoreEntryPoint The entry point of the PEI core.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS SecCoreImageBase;\r
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+\r
+ //\r
+ // Find SEC Core and PEI Core image base\r
+ //\r
+ Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
+ //\r
+ // Report SEC Core debug information when remote debug is enabled\r
+ //\r
+ ImageContext.ImageAddress = SecCoreImageBase;\r
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+ //\r
+ // Report PEI Core debug information when remote debug is enabled\r
+ //\r
+ ImageContext.ImageAddress = PeiCoreImageBase;\r
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+ //\r
+ // Find PEI Core entry point\r
+ //\r
+ Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);\r
+ if (EFI_ERROR (Status)) {\r
+ *PeiCoreEntryPoint = 0;\r
+ }\r
+\r
+ return;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ This PEIM will be invoked twice by pei core. In 1st entry, it will call FspInit API.\r
+ In 2nd entry, it will parse the hoblist from fsp and report them into pei core.\r
+ This file contains the main entrypoint of the PEIM.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "FspInitPei.h"\r
+\r
+/**\r
+ FSP Init continuation function.\r
+ Control will be returned to this callback function after FspInit API call.\r
+\r
+ @param[in] Status Status of the FSP INIT API\r
+ @param[in] HobListPtr Pointer to the HOB data structure defined in the PI specification.\r
+\r
+**/\r
+VOID\r
+ContinuationFunc (\r
+ IN FSP_STATUS Status,\r
+ IN VOID *HobListPtr\r
+ )\r
+{\r
+ EFI_BOOT_MODE BootMode;\r
+ UINT64 StackSize;\r
+ EFI_PHYSICAL_ADDRESS StackBase;\r
+\r
+ DEBUG ((DEBUG_INFO, "ContinuationFunc - %r\n", Status));\r
+ DEBUG ((DEBUG_INFO, "HobListPtr - 0x%x\n", HobListPtr));\r
+\r
+ if (Status != FSP_SUCCESS) {\r
+ CpuDeadLoop ();\r
+ }\r
+\r
+ //\r
+ // Can not call any PeiServices\r
+ //\r
+ BootMode = GetBootMode ();\r
+\r
+ GetStackInfo (BootMode, TRUE, &StackBase, &StackSize);\r
+ DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", StackBase));\r
+ DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", StackSize));\r
+ CallPeiCoreEntryPoint (\r
+ HobListPtr,\r
+ (VOID *)(UINTN)StackBase,\r
+ (VOID *)(UINTN)(StackBase + StackSize)\r
+ );\r
+}\r
+\r
+/**\r
+ Call FspInit API.\r
+\r
+ @param[in] FspHeader FSP header pointer.\r
+**/\r
+VOID\r
+SecFspInit (\r
+ IN FSP_INFO_HEADER *FspHeader\r
+ )\r
+{\r
+ FSP_INIT_PARAMS FspInitParams;\r
+ FSP_INIT_RT_COMMON_BUFFER FspRtBuffer;\r
+ UINT8 FspUpdRgn[FixedPcdGet32 (PcdMaxUpdRegionSize)];\r
+ UINT32 UpdRegionSize;\r
+ EFI_BOOT_MODE BootMode;\r
+ UINT64 StackSize;\r
+ EFI_PHYSICAL_ADDRESS StackBase;\r
+ FSP_STATUS FspStatus;\r
+\r
+ DEBUG ((DEBUG_INFO, "SecFspInit enter\n"));\r
+\r
+ PeiServicesGetBootMode (&BootMode);\r
+ DEBUG ((DEBUG_INFO, "BootMode - 0x%x\n", BootMode));\r
+\r
+ GetStackInfo (BootMode, FALSE, &StackBase, &StackSize);\r
+ DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", StackBase));\r
+ DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", StackSize));\r
+\r
+ ZeroMem (&FspRtBuffer, sizeof(FspRtBuffer));\r
+ FspRtBuffer.StackTop = (UINT32 *)(UINTN)(StackBase + StackSize);\r
+\r
+ FspRtBuffer.BootMode = BootMode;\r
+\r
+ /* Platform override any UPD configs */\r
+ UpdRegionSize = GetUpdRegionSize();\r
+ DEBUG ((DEBUG_INFO, "UpdRegionSize - 0x%x\n", UpdRegionSize));\r
+ DEBUG ((DEBUG_INFO, "sizeof(FspUpdRgn) - 0x%x\n", sizeof(FspUpdRgn)));\r
+ ASSERT(sizeof(FspUpdRgn) >= UpdRegionSize);\r
+ ZeroMem (FspUpdRgn, UpdRegionSize);\r
+ FspRtBuffer.UpdDataRgnPtr = UpdateFspUpdConfigs (FspUpdRgn);\r
+\r
+ ZeroMem (&FspInitParams, sizeof(FspInitParams));\r
+ FspInitParams.NvsBufferPtr = GetNvsBuffer ();\r
+ DEBUG ((DEBUG_INFO, "NvsBufferPtr - 0x%x\n", FspInitParams.NvsBufferPtr));\r
+ FspInitParams.RtBufferPtr = (VOID *)&FspRtBuffer;\r
+ FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ContinuationFunc;\r
+\r
+ SaveSecContext (GetPeiServicesTablePointer ());\r
+\r
+ DEBUG ((DEBUG_INFO, "FspInitParams - 0x%x\n", &FspInitParams));\r
+ DEBUG ((DEBUG_INFO, " NvsBufferPtr - 0x%x\n", FspInitParams.NvsBufferPtr));\r
+ DEBUG ((DEBUG_INFO, " RtBufferPtr - 0x%x\n", FspInitParams.RtBufferPtr));\r
+ DEBUG ((DEBUG_INFO, " StackTop - 0x%x\n", FspRtBuffer.StackTop));\r
+ DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", FspRtBuffer.BootMode));\r
+ DEBUG ((DEBUG_INFO, " UpdDataRgnPtr - 0x%x\n", FspRtBuffer.UpdDataRgnPtr));\r
+ DEBUG ((DEBUG_INFO, " ContinuationFunc - 0x%x\n", FspInitParams.ContinuationFunc));\r
+\r
+ FspStatus = CallFspInit (FspHeader, &FspInitParams);\r
+ //\r
+ // Should never return\r
+ //\r
+ DEBUG((DEBUG_ERROR, "FSP Init failed, status: 0x%x\n", FspStatus));\r
+ CpuDeadLoop ();\r
+}\r
+\r
+/**\r
+ This is the entrypoint of PEIM\r
+\r
+ @param[in] FileHandle Handle of the file being invoked.\r
+ @param[in] PeiServices Describes the list of possible PEI Services.\r
+\r
+ @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspPeiEntryPoint (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ FSP_INFO_HEADER *FspHeader;\r
+ EFI_STATUS Status;\r
+ FSP_INIT_DONE_PPI *FspInitDone;\r
+ VOID *FspHobList;\r
+ EFI_BOOT_MODE BootMode;\r
+\r
+ DEBUG ((DEBUG_INFO, "FspPeiEntryPoint\n"));\r
+\r
+ Status = PeiServicesLocatePpi (\r
+ &gFspInitDonePpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &FspInitDone\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // 1st entry\r
+ //\r
+ DEBUG ((DEBUG_INFO, "1st entry\n"));\r
+ FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+ DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", FspHeader));\r
+ if (FspHeader == NULL) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ SecFspInit (FspHeader);\r
+\r
+ //\r
+ // Never return here\r
+ //\r
+ CpuDeadLoop ();\r
+ } else {\r
+ //\r
+ // 2nd entry\r
+ //\r
+ DEBUG ((DEBUG_INFO, "2nd entry\n"));\r
+ Status = FspInitDone->GetFspHobList (PeiServices, FspInitDone, &FspHobList);\r
+ DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));\r
+ FspHobProcess (FspHobList);\r
+\r
+ PeiServicesGetBootMode (&BootMode);\r
+ if (BootMode == BOOT_ON_S3_RESUME) {\r
+ Status = PeiServicesNotifyPpi (&mS3EndOfPeiNotifyDesc);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ This is PEIM header file.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FSP_INIT_PEI_H_\r
+#define _FSP_INIT_PEI_H_\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/FspPlatformInfoLib.h>\r
+#include <Library/FspPlatformSecLib.h>\r
+#include <Library/FspHobProcessLib.h>\r
+#include <Library/FspApiLib.h>\r
+\r
+#include <Ppi/FspInitDone.h>\r
+#include <Ppi/EndOfPeiPhase.h>\r
+\r
+extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# FSP PEI Module\r
+#\r
+# This PEIM will be invoked twice by pei core. In 1st entry, it will call FspInit API.\r
+# In 2nd entry, it will parse the hoblist from fsp and report them into pei core.\r
+# including install the memory as required.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FspInitPeim\r
+ FILE_GUID = BC59E2E1-7492-4031-806E-C48DCCC3A026\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = FspPeiEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ FspInitPei.c\r
+ FspInitPei.h\r
+ FspNotifyS3.c\r
+ SecMain.c\r
+ SecMain.h\r
+ FindPeiCore.c\r
+ SecFspInitDone.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ PeiServicesLib\r
+ PeiServicesTablePointerLib\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ HobLib\r
+ FspPlatformInfoLib\r
+ FspHobProcessLib\r
+ FspPlatformSecLib\r
+ DebugAgentLib\r
+ UefiCpuLib\r
+ PeCoffGetEntryPointLib\r
+ PeCoffExtraActionLib\r
+ FspApiLib\r
+\r
+[Ppis]\r
+ gTopOfTemporaryRamPpiGuid\r
+ gFspInitDonePpiGuid\r
+ gEfiEndOfPeiSignalPpiGuid\r
+\r
+[FixedPcd]\r
+ gFspWrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported\r
+\r
+[Pcd]\r
+ gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize\r
+ gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize\r
+\r
+[Depex]\r
+ gEfiPeiMasterBootModePpiGuid\r
--- /dev/null
+/** @file\r
+ In EndOfPei notify, it will call FspNotifyPhase API.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "FspInitPei.h"\r
+\r
+/**\r
+ This function handles S3 resume task at the end of PEI\r
+\r
+ @param[in] PeiServices Pointer to PEI Services Table.\r
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that\r
+ caused this function to execute.\r
+ @param[in] Ppi Pointer to the PPI data associated with this function.\r
+\r
+ @retval EFI_STATUS Always return EFI_SUCCESS\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+S3EndOfPeiNotify (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,\r
+ IN VOID *Ppi\r
+ );\r
+\r
+EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiEndOfPeiSignalPpiGuid,\r
+ S3EndOfPeiNotify\r
+};\r
+\r
+/**\r
+ This function handles S3 resume task at the end of PEI\r
+\r
+ @param[in] PeiServices Pointer to PEI Services Table.\r
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that\r
+ caused this function to execute.\r
+ @param[in] Ppi Pointer to the PPI data associated with this function.\r
+\r
+ @retval EFI_STATUS Always return EFI_SUCCESS\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+S3EndOfPeiNotify (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,\r
+ IN VOID *Ppi\r
+ )\r
+{\r
+ NOTIFY_PHASE_PARAMS NotifyPhaseParams;\r
+ FSP_STATUS FspStatus;\r
+ FSP_INFO_HEADER *FspHeader;\r
+\r
+ FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+ if (FspHeader == NULL) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ NotifyPhaseParams.Phase = EnumInitPhaseAfterPciEnumeration;\r
+ FspStatus = CallFspNotifyPhase (FspHeader, &NotifyPhaseParams);\r
+ if (FspStatus != FSP_SUCCESS) {\r
+ DEBUG((DEBUG_ERROR, "FSP S3NotifyPhase AfterPciEnumeration failed, status: 0x%x\n", FspStatus));\r
+ } else {\r
+ DEBUG((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration Success.\n"));\r
+ }\r
+\r
+ NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;\r
+ FspStatus = CallFspNotifyPhase (FspHeader, &NotifyPhaseParams);\r
+ if (FspStatus != FSP_SUCCESS) {\r
+ DEBUG((DEBUG_ERROR, "FSP S3NotifyPhase ReadyToBoot failed, status: 0x%x\n", FspStatus));\r
+ } else {\r
+ DEBUG((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot Success.\n"));\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ Install FspInitDone PPI and GetFspHobList API.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "SecMain.h"\r
+\r
+FSP_INIT_DONE_PPI gFspInitDonePpi = {\r
+ FspInitDoneGetFspHobList\r
+};\r
+\r
+/**\r
+ Return Hob list produced by FSP.\r
+\r
+ @param[in] PeiServices The pointer to the PEI Services Table.\r
+ @param[in] This The pointer to this instance of this PPI.\r
+ @param[out] FspHobList The pointer to Hob list produced by FSP.\r
+\r
+ @return EFI_SUCCESS FReturn Hob list produced by FSP successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspInitDoneGetFspHobList (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN FSP_INIT_DONE_PPI *This,\r
+ OUT VOID **FspHobList\r
+ )\r
+{\r
+ VOID *TopOfTemporaryRamPpi;\r
+ EFI_STATUS Status;\r
+\r
+ Status = (*PeiServices)->LocatePpi (\r
+ PeiServices,\r
+ &gTopOfTemporaryRamPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &TopOfTemporaryRamPpi\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ *FspHobList = (VOID *)(UINTN)(*(UINT32 *)((UINTN)TopOfTemporaryRamPpi - sizeof(UINT32)));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ C functions in SEC\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "SecMain.h"\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPeiSecMainPpi[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &gTopOfTemporaryRamPpiGuid,\r
+ NULL // To be patched later.\r
+ },\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gFspInitDonePpiGuid,\r
+ &gFspInitDonePpi\r
+ },\r
+};\r
+\r
+//\r
+// These are IDT entries pointing to 10:FFFFFFE4h.\r
+//\r
+UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;\r
+\r
+/**\r
+ Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] Context The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+ IN VOID *Context\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] SizeOfRam Size of the temporary memory available for use.\r
+ @param[in] TempRamBase Base address of tempory ram\r
+ @param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ SEC_IDT_TABLE IdtTableInStack;\r
+ UINT32 Index;\r
+ UINT32 PeiStackSize;\r
+\r
+ PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);\r
+ if (PeiStackSize == 0) {\r
+ PeiStackSize = (SizeOfRam >> 1);\r
+ }\r
+\r
+ ASSERT (PeiStackSize < SizeOfRam);\r
+\r
+ //\r
+ // Process all libraries constructor function linked to SecCore.\r
+ //\r
+ ProcessLibraryConstructorList ();\r
+\r
+ DEBUG ((DEBUG_INFO, "FspPei - SecStartup\n"));\r
+\r
+ //\r
+ // Initialize floating point operating environment\r
+ // to be compliant with UEFI spec.\r
+ //\r
+ InitializeFloatingPointUnits ();\r
+\r
+\r
+ // |-------------------|---->\r
+ // |Idt Table |\r
+ // |-------------------|\r
+ // |PeiService Pointer | PeiStackSize\r
+ // |-------------------|\r
+ // | |\r
+ // | Stack |\r
+ // |-------------------|---->\r
+ // | |\r
+ // | |\r
+ // | Heap | PeiTemporayRamSize\r
+ // | |\r
+ // | |\r
+ // |-------------------|----> TempRamBase\r
+\r
+ IdtTableInStack.PeiService = 0;\r
+ for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {\r
+ CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));\r
+ }\r
+\r
+ IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;\r
+ IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
+\r
+ AsmWriteIdtr (&IdtDescriptor);\r
+\r
+ //\r
+ // Update the base address and length of Pei temporary memory\r
+ //\r
+ SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
+ SecCoreData.BootFirmwareVolumeSize = (UINTN)(SIZE_4GB - (UINTN) BootFirmwareVolume);\r
+ SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;\r
+ SecCoreData.TemporaryRamSize = SizeOfRam;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;\r
+ SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackSize = PeiStackSize;\r
+\r
+ DEBUG ((DEBUG_INFO, "BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));\r
+ DEBUG ((DEBUG_INFO, "BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));\r
+ DEBUG ((DEBUG_INFO, "TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase));\r
+ DEBUG ((DEBUG_INFO, "TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize));\r
+ DEBUG ((DEBUG_INFO, "PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase));\r
+ DEBUG ((DEBUG_INFO, "PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize));\r
+ DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", SecCoreData.StackBase));\r
+ DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", SecCoreData.StackSize));\r
+\r
+ //\r
+ // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
+ //\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);\r
+\r
+}\r
+\r
+/**\r
+ This API patch the TopOfTemporaryRam value in SecPpiList.\r
+\r
+ @param[in,out] SecPpiList PPI list to be patched.\r
+ @param[in] TopOfTemporaryRam The top of Temporary Ram.\r
+\r
+**/\r
+VOID\r
+PatchTopOfTemporaryRamPpi (\r
+ IN OUT EFI_PEI_PPI_DESCRIPTOR *SecPpiList,\r
+ IN VOID *TopOfTemporaryRam\r
+ )\r
+{\r
+ SecPpiList[0].Ppi = TopOfTemporaryRam;\r
+}\r
+\r
+/**\r
+ Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] Context The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+ IN VOID *Context\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF *SecCoreData;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINT32 Index;\r
+ EFI_PEI_PPI_DESCRIPTOR LocalSecPpiList[sizeof(mPeiSecMainPpi)/sizeof(mPeiSecMainPpi[0])];\r
+ EFI_PEI_PPI_DESCRIPTOR AllSecPpiList[FixedPcdGet32(PcdSecCoreMaxPpiSupported)];\r
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;\r
+\r
+ SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;\r
+ //\r
+ // Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug\r
+ // is enabled.\r
+ //\r
+ FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);\r
+ if (PeiCoreEntryPoint == NULL)\r
+ {\r
+ CpuDeadLoop ();\r
+ }\r
+\r
+ CopyMem (LocalSecPpiList, mPeiSecMainPpi, sizeof(mPeiSecMainPpi));\r
+ PatchTopOfTemporaryRamPpi (LocalSecPpiList, (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize));\r
+\r
+ //\r
+ // Perform platform specific initialization before entering PeiCore.\r
+ //\r
+ PpiList = SecPlatformMain (SecCoreData);\r
+ if (PpiList != NULL) {\r
+ //\r
+ // Remove the terminal flag from the terminal Ppi\r
+ //\r
+ CopyMem (AllSecPpiList, LocalSecPpiList, sizeof (LocalSecPpiList));\r
+ for (Index = 0; Index < PcdGet32 (PcdSecCoreMaxPpiSupported); Index ++) {\r
+ if ((AllSecPpiList[Index].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) == EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) {\r
+ break;\r
+ }\r
+ }\r
+ AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
+\r
+ //\r
+ // Append the platform additional Ppi list\r
+ //\r
+ Index += 1;\r
+ while (Index < PcdGet32 (PcdSecCoreMaxPpiSupported) &&\r
+ ((PpiList->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST)) {\r
+ CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+ Index++;\r
+ PpiList++;\r
+ }\r
+\r
+ //\r
+ // Check whether the total Ppis exceeds the max supported Ppi.\r
+ //\r
+ if (Index >= PcdGet32 (PcdSecCoreMaxPpiSupported)) {\r
+ //\r
+ // the total Ppi is larger than the supported Max\r
+ // PcdSecCoreMaxPpiSupported can be enlarged to solve it.\r
+ //\r
+ CpuDeadLoop ();\r
+ } else {\r
+ //\r
+ // Add the terminal Ppi\r
+ //\r
+ CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+ }\r
+\r
+ //\r
+ // Set PpiList to the total Ppi\r
+ //\r
+ PpiList = &AllSecPpiList[0];\r
+ } else {\r
+ //\r
+ // No addition Ppi, PpiList directly point to the common Ppi list.\r
+ //\r
+ PpiList = &LocalSecPpiList[0];\r
+ }\r
+\r
+ //\r
+ // Transfer the control to the PEI core\r
+ //\r
+ ASSERT (PeiCoreEntryPoint != NULL);\r
+ (*PeiCoreEntryPoint) (SecCoreData, PpiList);\r
+\r
+ //\r
+ // Should not come here.\r
+ //\r
+ return ;\r
+}\r
--- /dev/null
+/** @file\r
+ Master header file for SecCore.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SEC_CORE_H_\r
+#define _SEC_CORE_H_\r
+\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+#include <Ppi/FspInitDone.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/FspPlatformSecLib.h>\r
+#include <Library/FspPlatformInfoLib.h>\r
+#include <Library/UefiCpuLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/PeCoffExtraActionLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+#include <FspApi.h>\r
+#include <FspInfoHeader.h>\r
+\r
+#define SEC_IDT_ENTRY_COUNT 34\r
+\r
+typedef struct _SEC_IDT_TABLE {\r
+ //\r
+ // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base\r
+ // address should be 8-byte alignment.\r
+ // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
+ // EFI_PEI_SERVICES**\r
+ //\r
+ UINT64 PeiService;\r
+ UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];\r
+} SEC_IDT_TABLE;\r
+\r
+/**\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] SizeOfRam Size of the temporary memory available for use.\r
+ @param[in] TempRamBase Base address of tempory ram\r
+ @param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume\r
+ );\r
+\r
+/**\r
+ Find and return Pei Core entry point.\r
+\r
+ It also find SEC and PEI Core file debug inforamtion. It will report them if\r
+ remote debug is enabled.\r
+\r
+ @param[in] BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param[out] PeiCoreEntryPoint Point to the PEI core entry point.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint\r
+ );\r
+\r
+/**\r
+ Autogenerated function that calls the library constructors for all of the module's\r
+ dependent libraries. This function must be called by the SEC Core once a stack has\r
+ been established.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessLibraryConstructorList (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Return Hob list produced by FSP.\r
+\r
+ @param[in] PeiServices The pointer to the PEI Services Table.\r
+ @param[in] This The pointer to this instance of this PPI.\r
+ @param[out] FspHobList The pointer to Hob list produced by FSP.\r
+\r
+ @return EFI_SUCCESS FReturn Hob list produced by FSP successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspInitDoneGetFspHobList (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN FSP_INIT_DONE_PPI *This,\r
+ OUT VOID **FspHobList\r
+ );\r
+\r
+extern FSP_INIT_DONE_PPI gFspInitDonePpi;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This driver will register two callbacks to call fsp's notifies.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/PciEnumerationComplete.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/FspApiLib.h>\r
+\r
+FSP_INFO_HEADER *mFspHeader = NULL;\r
+\r
+/**\r
+ PciEnumerationComplete Protocol notification event handler.\r
+\r
+ @param[in] Event Event whose notification function is being invoked.\r
+ @param[in] Context Pointer to the notification function's context.\r
+**/\r
+VOID\r
+EFIAPI\r
+OnPciEnumerationComplete (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ NOTIFY_PHASE_PARAMS NotifyPhaseParams;\r
+ EFI_STATUS Status;\r
+ FSP_STATUS FspStatus;\r
+ VOID *Interface;\r
+\r
+ //\r
+ // Try to locate it because gEfiPciEnumerationCompleteProtocolGuid will trigger it once when registration.\r
+ // Just return if it is not found.\r
+ //\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiPciEnumerationCompleteProtocolGuid,\r
+ NULL,\r
+ &Interface\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return ;\r
+ }\r
+\r
+ NotifyPhaseParams.Phase = EnumInitPhaseAfterPciEnumeration;\r
+ FspStatus = CallFspNotifyPhase (mFspHeader, &NotifyPhaseParams);\r
+ if (FspStatus != FSP_SUCCESS) {\r
+ DEBUG((DEBUG_ERROR, "FSP NotifyPhase AfterPciEnumeration failed, status: 0x%x\n", FspStatus));\r
+ } else {\r
+ DEBUG((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration Success.\n"));\r
+ }\r
+}\r
+\r
+/**\r
+ Notification function of EVT_GROUP_READY_TO_BOOT event group.\r
+\r
+ This is a notification function registered on EVT_GROUP_READY_TO_BOOT event group.\r
+ When the Boot Manager is about to load and execute a boot option, it reclaims variable\r
+ storage if free size is below the threshold.\r
+\r
+ @param[in] Event Event whose notification function is being invoked.\r
+ @param[in] Context Pointer to the notification function's context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+OnReadyToBoot (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ NOTIFY_PHASE_PARAMS NotifyPhaseParams;\r
+ FSP_STATUS FspStatus;\r
+\r
+ gBS->CloseEvent (Event);\r
+\r
+ NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;\r
+ FspStatus = CallFspNotifyPhase (mFspHeader, &NotifyPhaseParams);\r
+ if (FspStatus != FSP_SUCCESS) {\r
+ DEBUG((DEBUG_ERROR, "FSP NotifyPhase ReadyToBoot failed, status: 0x%x\n", FspStatus));\r
+ } else {\r
+ DEBUG((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot Success.\n"));\r
+ }\r
+}\r
+\r
+/**\r
+ Main entry for the FSP DXE module.\r
+\r
+ This routine registers two callbacks to call fsp's notifies.\r
+\r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
+ @param[in] SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS The entry point is executed successfully.\r
+ @retval other Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspDxeEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_EVENT ReadyToBootEvent;\r
+ VOID *Registration;\r
+ EFI_EVENT ProtocolNotifyEvent;\r
+\r
+ mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+ DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", mFspHeader));\r
+ if (mFspHeader == NULL) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ ProtocolNotifyEvent = EfiCreateProtocolNotifyEvent (\r
+ &gEfiPciEnumerationCompleteProtocolGuid,\r
+ TPL_CALLBACK,\r
+ OnPciEnumerationComplete,\r
+ NULL,\r
+ &Registration\r
+ );\r
+ ASSERT (ProtocolNotifyEvent != NULL);\r
+\r
+ Status = EfiCreateEventReadyToBootEx (\r
+ TPL_CALLBACK,\r
+ OnReadyToBoot,\r
+ NULL,\r
+ &ReadyToBootEvent\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# FSP DXE Module\r
+#\r
+# This driver will register two callbacks to call fsp's notifies.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FspNotifyDxe\r
+ FILE_GUID = 8714C537-6D4B-4247-AA6C-29E8495F9100\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = FspDxeEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ FspNotifyDxe.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ DebugLib\r
+ BaseMemoryLib\r
+ UefiLib\r
+ FspApiLib\r
+\r
+[Protocols]\r
+ gEfiPciEnumerationCompleteProtocolGuid\r
+\r
+[Pcd]\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+ Locate the entry point for the PEI Core\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+\r
+#include "SecMain.h"\r
+\r
+/**\r
+ Find core image base.\r
+\r
+ @param[in] BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param[out] SecCoreImageBase The base address of the SEC core image.\r
+ @param[out] PeiCoreImageBase The base address of the PEI core image.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FindImageBase (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,\r
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase\r
+ )\r
+{\r
+ EFI_PHYSICAL_ADDRESS CurrentAddress;\r
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;\r
+ EFI_FFS_FILE_HEADER *File;\r
+ UINT32 Size;\r
+ EFI_PHYSICAL_ADDRESS EndOfFile;\r
+ EFI_COMMON_SECTION_HEADER *Section;\r
+ EFI_PHYSICAL_ADDRESS EndOfSection;\r
+\r
+ *SecCoreImageBase = 0;\r
+ *PeiCoreImageBase = 0;\r
+\r
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;\r
+ EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;\r
+\r
+ //\r
+ // Loop through the FFS files in the Boot Firmware Volume\r
+ //\r
+ for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {\r
+\r
+ CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;\r
+ if (CurrentAddress > EndOfFirmwareVolume) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;\r
+ if (IS_FFS_FILE2 (File)) {\r
+ Size = FFS_FILE2_SIZE (File);\r
+ if (Size <= 0x00FFFFFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ } else {\r
+ Size = FFS_FILE_SIZE (File);\r
+ if (Size < sizeof (EFI_FFS_FILE_HEADER)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ EndOfFile = CurrentAddress + Size;\r
+ if (EndOfFile > EndOfFirmwareVolume) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Look for SEC Core / PEI Core files\r
+ //\r
+ if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&\r
+ File->Type != EFI_FV_FILETYPE_PEI_CORE) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Loop through the FFS file sections within the FFS file\r
+ //\r
+ if (IS_FFS_FILE2 (File)) {\r
+ EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));\r
+ } else {\r
+ EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));\r
+ }\r
+ for (;;) {\r
+ CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;\r
+ Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;\r
+\r
+ if (IS_SECTION2 (Section)) {\r
+ Size = SECTION2_SIZE (Section);\r
+ if (Size <= 0x00FFFFFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ } else {\r
+ Size = SECTION_SIZE (Section);\r
+ if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ EndOfSection = CurrentAddress + Size;\r
+ if (EndOfSection > EndOfFile) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Look for executable sections\r
+ //\r
+ if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {\r
+ if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {\r
+ if (IS_SECTION2 (Section)) {\r
+ *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+ } else {\r
+ *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+ }\r
+ } else {\r
+ if (IS_SECTION2 (Section)) {\r
+ *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+ } else {\r
+ *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Both SEC Core and PEI Core images found\r
+ //\r
+ if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Find and return Pei Core entry point.\r
+\r
+ It also find SEC and PEI Core file debug inforamtion. It will report them if\r
+ remote debug is enabled.\r
+\r
+ @param[in] BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param[out] PeiCoreEntryPoint The entry point of the PEI core.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS SecCoreImageBase;\r
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+\r
+ //\r
+ // Find SEC Core and PEI Core image base\r
+ //\r
+ Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
+ //\r
+ // Report SEC Core debug information when remote debug is enabled\r
+ //\r
+ ImageContext.ImageAddress = SecCoreImageBase;\r
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+ //\r
+ // Report PEI Core debug information when remote debug is enabled\r
+ //\r
+ ImageContext.ImageAddress = PeiCoreImageBase;\r
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+ //\r
+ // Find PEI Core entry point\r
+ //\r
+ Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);\r
+ if (EFI_ERROR (Status)) {\r
+ *PeiCoreEntryPoint = 0;\r
+ }\r
+\r
+ return;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# This is the first module taking control of the platform upon power-on/reset.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FspWrapperSecCore\r
+ FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ SecMain.c\r
+ SecMain.h\r
+ FindPeiCore.c\r
+\r
+[Sources.IA32]\r
+ Ia32/ResetVec.asm16 | MSFT\r
+ Ia32/ResetVec.asm16 | INTEL\r
+ Ia32/Dummy.asm\r
+\r
+[Binaries.Ia32]\r
+ RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ FspPlatformInfoLib\r
+ FspPlatformSecLib\r
+ DebugAgentLib\r
+ UefiCpuLib\r
+ PeCoffGetEntryPointLib\r
+ PeCoffExtraActionLib\r
+\r
+[Ppis]\r
+ gTopOfTemporaryRamPpiGuid\r
+\r
+[FixedPcd]\r
+ gFspWrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported\r
+\r
+[Pcd]\r
+ gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Dummy.asm\r
+;\r
+; Abstract:\r
+;\r
+; To pass build\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .586p\r
+ .model flat,C\r
+ .code\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ResetVec.asm\r
+;\r
+; Abstract:\r
+;\r
+; Reset Vector Data structure\r
+; This structure is located at 0xFFFFFFC0\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .model tiny\r
+ .686p\r
+ .stack 0h\r
+ .code\r
+\r
+;\r
+; The layout of this file is fixed. The build tool makes assumption of the layout.\r
+;\r
+\r
+ ORG 0h\r
+;\r
+; Reserved\r
+;\r
+ReservedData DD 0eeeeeeeeh, 0eeeeeeeeh\r
+\r
+ ORG 10h\r
+;\r
+; This is located at 0xFFFFFFD0h\r
+;\r
+ mov di, "AP"\r
+ jmp ApStartup\r
+\r
+ ORG 20h\r
+;\r
+; Pointer to the entry point of the PEI core\r
+; It is located at 0xFFFFFFE0, and is fixed up by some build tool\r
+; So if the value 8..1 appears in the final FD image, tool failure occurs.\r
+;\r
+PeiCoreEntryPoint DD 87654321h\r
+\r
+;\r
+; This is the handler for all kinds of exceptions. Since it's for debugging\r
+; purpose only, nothing except a deadloop would be done here. Developers could\r
+; analyze the cause of the exception if a debugger had been attached.\r
+;\r
+InterruptHandler PROC\r
+ jmp $\r
+ iret\r
+InterruptHandler ENDP\r
+\r
+ ORG 30h\r
+;\r
+; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte\r
+; Execution starts here upon power-on/platform-reset.\r
+;\r
+ResetHandler:\r
+ nop\r
+ nop\r
+ApStartup:\r
+ ;\r
+ ; Jmp Rel16 instruction\r
+ ; Use machine code directly in case of the assembler optimization\r
+ ; SEC entry point relatvie address will be fixed up by some build tool.\r
+ ;\r
+ ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in\r
+ ; SecEntry.asm\r
+ ;\r
+ DB 0e9h\r
+ DW -3\r
+\r
+\r
+ ORG 38h\r
+;\r
+; Ap reset vector segment address is at 0xFFFFFFF8\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs\r
+;\r
+ApSegAddress dd 12345678h\r
+\r
+ ORG 3ch\r
+;\r
+; BFV Base is at 0xFFFFFFFC\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs.\r
+;\r
+BfvBase DD 12345678h\r
+\r
+;\r
+; Nothing can go here, otherwise the layout of this file would change.\r
+;\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ C functions in SEC\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "SecMain.h"\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPeiSecMainPpi[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gTopOfTemporaryRamPpiGuid,\r
+ NULL // To be patched later.\r
+ },\r
+};\r
+\r
+//\r
+// These are IDT entries pointing to 10:FFFFFFE4h.\r
+//\r
+UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;\r
+\r
+/**\r
+ Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] Context The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+ IN VOID *Context\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] SizeOfRam Size of the temporary memory available for use.\r
+ @param[in] TempRamBase Base address of tempory ram\r
+ @param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ SEC_IDT_TABLE IdtTableInStack;\r
+ UINT32 Index;\r
+ UINT32 PeiStackSize;\r
+\r
+ PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);\r
+ if (PeiStackSize == 0) {\r
+ PeiStackSize = (SizeOfRam >> 1);\r
+ }\r
+\r
+ ASSERT (PeiStackSize < SizeOfRam);\r
+\r
+ //\r
+ // Process all libraries constructor function linked to SecCore.\r
+ //\r
+ ProcessLibraryConstructorList ();\r
+\r
+ DEBUG ((DEBUG_INFO, "SecCore - SecStartup\n"));\r
+\r
+ //\r
+ // Initialize floating point operating environment\r
+ // to be compliant with UEFI spec.\r
+ //\r
+ InitializeFloatingPointUnits ();\r
+\r
+\r
+ // |-------------------|---->\r
+ // |Idt Table |\r
+ // |-------------------|\r
+ // |PeiService Pointer | PeiStackSize\r
+ // |-------------------|\r
+ // | |\r
+ // | Stack |\r
+ // |-------------------|---->\r
+ // | |\r
+ // | |\r
+ // | Heap | PeiTemporayRamSize\r
+ // | |\r
+ // | |\r
+ // |-------------------|----> TempRamBase\r
+\r
+ IdtTableInStack.PeiService = 0;\r
+ for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {\r
+ CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));\r
+ }\r
+\r
+ IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;\r
+ IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
+\r
+ AsmWriteIdtr (&IdtDescriptor);\r
+\r
+ //\r
+ // Update the base address and length of Pei temporary memory\r
+ //\r
+ SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
+ SecCoreData.BootFirmwareVolumeSize = (UINTN)(SIZE_4GB - (UINTN) BootFirmwareVolume);\r
+ SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;\r
+ SecCoreData.TemporaryRamSize = SizeOfRam;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;\r
+ SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackSize = PeiStackSize;\r
+\r
+ DEBUG ((DEBUG_INFO, "BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));\r
+ DEBUG ((DEBUG_INFO, "BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));\r
+ DEBUG ((DEBUG_INFO, "TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase));\r
+ DEBUG ((DEBUG_INFO, "TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize));\r
+ DEBUG ((DEBUG_INFO, "PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase));\r
+ DEBUG ((DEBUG_INFO, "PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize));\r
+ DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", SecCoreData.StackBase));\r
+ DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", SecCoreData.StackSize));\r
+\r
+ //\r
+ // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
+ //\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);\r
+\r
+}\r
+\r
+/**\r
+ This API patch the TopOfTemporaryRam value in SecPpiList.\r
+\r
+ @param[in,out] SecPpiList PPI list to be patched.\r
+ @param[in] TopOfTemporaryRam The top of CAR.\r
+\r
+**/\r
+VOID\r
+PatchTopOfTemporaryRamPpi (\r
+ IN OUT EFI_PEI_PPI_DESCRIPTOR *SecPpiList,\r
+ IN VOID *TopOfTemporaryRam\r
+ )\r
+{\r
+ SecPpiList[0].Ppi = TopOfTemporaryRam;\r
+}\r
+\r
+/**\r
+ Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] Context The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+ IN VOID *Context\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF *SecCoreData;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINT32 Index;\r
+ EFI_PEI_PPI_DESCRIPTOR LocalSecPpiList[sizeof(mPeiSecMainPpi)/sizeof(mPeiSecMainPpi[0])];\r
+ EFI_PEI_PPI_DESCRIPTOR AllSecPpiList[FixedPcdGet32(PcdSecCoreMaxPpiSupported)];\r
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;\r
+\r
+ SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;\r
+ //\r
+ // Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug\r
+ // is enabled.\r
+ //\r
+ FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);\r
+ if (PeiCoreEntryPoint == NULL)\r
+ {\r
+ CpuDeadLoop ();\r
+ }\r
+\r
+ CopyMem (LocalSecPpiList, mPeiSecMainPpi, sizeof(mPeiSecMainPpi));\r
+ PatchTopOfTemporaryRamPpi (LocalSecPpiList, (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize));\r
+\r
+ //\r
+ // Perform platform specific initialization before entering PeiCore.\r
+ //\r
+ PpiList = SecPlatformMain (SecCoreData);\r
+ if (PpiList != NULL) {\r
+ //\r
+ // Remove the terminal flag from the terminal Ppi\r
+ //\r
+ CopyMem (AllSecPpiList, LocalSecPpiList, sizeof (LocalSecPpiList));\r
+ for (Index = 0; Index < PcdGet32 (PcdSecCoreMaxPpiSupported); Index ++) {\r
+ if ((AllSecPpiList[Index].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) == EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) {\r
+ break;\r
+ }\r
+ }\r
+ AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
+\r
+ //\r
+ // Append the platform additional Ppi list\r
+ //\r
+ Index += 1;\r
+ while (Index < PcdGet32 (PcdSecCoreMaxPpiSupported) &&\r
+ ((PpiList->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST)) {\r
+ CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+ Index++;\r
+ PpiList++;\r
+ }\r
+\r
+ //\r
+ // Check whether the total Ppis exceeds the max supported Ppi.\r
+ //\r
+ if (Index >= PcdGet32 (PcdSecCoreMaxPpiSupported)) {\r
+ //\r
+ // the total Ppi is larger than the supported Max\r
+ // PcdSecCoreMaxPpiSupported can be enlarged to solve it.\r
+ //\r
+ CpuDeadLoop ();\r
+ } else {\r
+ //\r
+ // Add the terminal Ppi\r
+ //\r
+ CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+ }\r
+\r
+ //\r
+ // Set PpiList to the total Ppi\r
+ //\r
+ PpiList = &AllSecPpiList[0];\r
+ } else {\r
+ //\r
+ // No addition Ppi, PpiList directly point to the common Ppi list.\r
+ //\r
+ PpiList = &LocalSecPpiList[0];\r
+ }\r
+\r
+ //\r
+ // Transfer the control to the PEI core\r
+ //\r
+ ASSERT (PeiCoreEntryPoint != NULL);\r
+ (*PeiCoreEntryPoint) (SecCoreData, PpiList);\r
+\r
+ //\r
+ // Should not come here.\r
+ //\r
+ return ;\r
+}\r
--- /dev/null
+/** @file\r
+ Master header file for SecCore.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SEC_CORE_H_\r
+#define _SEC_CORE_H_\r
+\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/FspPlatformSecLib.h>\r
+#include <Library/FspPlatformInfoLib.h>\r
+#include <Library/UefiCpuLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/PeCoffExtraActionLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+#include <FspApi.h>\r
+#include <FspInfoHeader.h>\r
+\r
+#define SEC_IDT_ENTRY_COUNT 34\r
+\r
+typedef struct _SEC_IDT_TABLE {\r
+ //\r
+ // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base\r
+ // address should be 8-byte alignment.\r
+ // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
+ // EFI_PEI_SERVICES**\r
+ //\r
+ UINT64 PeiService;\r
+ UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];\r
+} SEC_IDT_TABLE;\r
+\r
+/**\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] SizeOfRam Size of the temporary memory available for use.\r
+ @param[in] TempRamBase Base address of tempory ram\r
+ @param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume\r
+ );\r
+\r
+/**\r
+ Find and return Pei Core entry point.\r
+\r
+ It also find SEC and PEI Core file debug inforamtion. It will report them if\r
+ remote debug is enabled.\r
+\r
+ @param[in] BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param[out] PeiCoreEntryPoint Point to the PEI core entry point.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint\r
+ );\r
+\r
+/**\r
+ Autogenerated function that calls the library constructors for all of the module's\r
+ dependent libraries. This function must be called by the SEC Core once a stack has\r
+ been established.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessLibraryConstructorList (\r
+ VOID\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Automate the process of building the various reset vector types\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+import glob\r
+import os\r
+import subprocess\r
+import sys\r
+\r
+def RunCommand(commandLine):\r
+ #print ' '.join(commandLine)\r
+ return subprocess.call(commandLine)\r
+\r
+for filename in glob.glob(os.path.join('Bin', '*.raw')):\r
+ os.remove(filename)\r
+\r
+arch = 'ia32'\r
+debugType = None\r
+output = os.path.join('Bin', 'ResetVec')\r
+output += '.' + arch\r
+if debugType is not None:\r
+ output += '.' + debugType\r
+output += '.raw'\r
+commandLine = (\r
+ 'nasm',\r
+ '-D', 'ARCH_%s' % arch.upper(),\r
+ '-D', 'DEBUG_%s' % str(debugType).upper(),\r
+ '-o', output,\r
+ 'ResetVectorCode.asm',\r
+ )\r
+ret = RunCommand(commandLine)\r
+print '\tASM\t' + output\r
+if ret != 0: sys.exit(ret)\r
+\r
+commandLine = (\r
+ 'python',\r
+ 'Tools/FixupForRawSection.py',\r
+ output,\r
+ )\r
+print '\tFIXUP\t' + output\r
+ret = RunCommand(commandLine)\r
+if ret != 0: sys.exit(ret)\r
+\r
--- /dev/null
+;; @file\r
+; Reset Vector Data structure\r
+; This structure is located at 0xFFFFFFC0\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;;\r
+\r
+BITS 16\r
+\r
+\r
+;\r
+; The layout of this file is fixed. The build tool makes assumption of the layout.\r
+;\r
+\r
+ORG 0x0\r
+;\r
+; Reserved\r
+;\r
+ReservedData: DD 0eeeeeeeeh, 0eeeeeeeeh\r
+\r
+ ; ORG 0x10\r
+ TIMES 0x10-($-$$) DB 0\r
+;\r
+; This is located at 0xFFFFFFD0h\r
+;\r
+ mov di, "AP"\r
+ jmp ApStartup\r
+\r
+ ; ORG 0x20\r
+\r
+ TIMES 0x20-($-$$) DB 0\r
+\r
+; Pointer to the entry point of the PEI core\r
+; It is located at 0xFFFFFFE0, and is fixed up by some build tool\r
+; So if the value 8..1 appears in the final FD image, tool failure occurs.\r
+;\r
+PeiCoreEntryPoint: DD 0x12345678\r
+\r
+;\r
+; This is the handler for all kinds of exceptions. Since it's for debugging\r
+; purpose only, nothing except a deadloop would be done here. Developers could\r
+; analyze the cause of the exception if a debugger had been attached.\r
+;\r
+InterruptHandler:\r
+ jmp $\r
+ iret\r
+\r
+ ; ORG 0x30\r
+ TIMES 0x30-($-$$) DB 0\r
+;\r
+; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte\r
+; Execution starts here upon power-on/platform-reset.\r
+;\r
+ResetHandler:\r
+ nop\r
+ nop\r
+\r
+ApStartup:\r
+ ;\r
+ ; Jmp Rel16 instruction\r
+ ; Use machine code directly in case of the assembler optimization\r
+ ; SEC entry point relatvie address will be fixed up by some build tool.\r
+ ;\r
+ ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in\r
+ ; SecEntry.asm\r
+ ;\r
+ DB 0x0e9\r
+ DW -3\r
+\r
+ ; ORG 0x38\r
+\r
+ TIMES 0x38-($-$$) DB 0\r
+;\r
+; Ap reset vector segment address is at 0xFFFFFFF8\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs\r
+;\r
+ApSegAddress: dd 0x12345678\r
+\r
+ ; ORG 0x3c\r
+ TIMES 0x3c-($-$$) DB 0\r
+;\r
+; BFV Base is at 0xFFFFFFFC\r
+; This will be fixed up by some build tool,\r
+; so if the value 1..8 appears in the final FD image,\r
+; tool failure occurs.\r
+;\r
+BfvBase: DD 0x12345678\r
+\r
+;\r
+; Nothing can go here, otherwise the layout of this file would change.\r
+;\r
+\r
+ ; END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+; @file\r
+; This file includes all other code files to assemble the reset vector code\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+%include "Ia16/ResetVec.asm16"\r
--- /dev/null
+## @file\r
+# Apply fixup to VTF binary image for FFS Raw section\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+\r
+import sys\r
+\r
+filename = sys.argv[1]\r
+\r
+if filename.lower().find('ia32') >= 0:\r
+ d = open(sys.argv[1], 'rb').read()\r
+ c = ((len(d) + 4 + 7) & ~7) - 4\r
+ if c > len(d):\r
+ c -= len(d)\r
+ f = open(sys.argv[1], 'wb')\r
+ f.write('\x90' * c)\r
+ f.write(d)\r
+ f.close()\r
+else:\r
+ from struct import pack\r
+\r
+ PAGE_PRESENT = 0x01\r
+ PAGE_READ_WRITE = 0x02\r
+ PAGE_USER_SUPERVISOR = 0x04\r
+ PAGE_WRITE_THROUGH = 0x08\r
+ PAGE_CACHE_DISABLE = 0x010\r
+ PAGE_ACCESSED = 0x020\r
+ PAGE_DIRTY = 0x040\r
+ PAGE_PAT = 0x080\r
+ PAGE_GLOBAL = 0x0100\r
+ PAGE_2M_MBO = 0x080\r
+ PAGE_2M_PAT = 0x01000\r
+\r
+ def NopAlign4k(s):\r
+ c = ((len(s) + 0xfff) & ~0xfff) - len(s)\r
+ return ('\x90' * c) + s\r
+\r
+ def PageDirectoryEntries4GbOf2MbPages(baseAddress):\r
+\r
+ s = ''\r
+ for i in range(0x800):\r
+ i = (\r
+ baseAddress + long(i << 21) +\r
+ PAGE_2M_MBO +\r
+ PAGE_CACHE_DISABLE +\r
+ PAGE_ACCESSED +\r
+ PAGE_DIRTY +\r
+ PAGE_READ_WRITE +\r
+ PAGE_PRESENT\r
+ )\r
+ s += pack('Q', i)\r
+ return s\r
+\r
+ def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):\r
+ s = ''\r
+ for i in range(0x200):\r
+ i = (\r
+ pdeBase +\r
+ (min(i, 3) << 12) +\r
+ PAGE_CACHE_DISABLE +\r
+ PAGE_ACCESSED +\r
+ PAGE_READ_WRITE +\r
+ PAGE_PRESENT\r
+ )\r
+ s += pack('Q', i)\r
+ return s\r
+\r
+ def PageMapLevel4Table4GbOf2MbPages(pdptBase):\r
+ s = ''\r
+ for i in range(0x200):\r
+ i = (\r
+ pdptBase +\r
+ (min(i, 0) << 12) +\r
+ PAGE_CACHE_DISABLE +\r
+ PAGE_ACCESSED +\r
+ PAGE_READ_WRITE +\r
+ PAGE_PRESENT\r
+ )\r
+ s += pack('Q', i)\r
+ return s\r
+\r
+ def First4GbPageEntries(topAddress):\r
+ PDE = PageDirectoryEntries4GbOf2MbPages(0L)\r
+ pml4tBase = topAddress - 0x1000\r
+ pdptBase = pml4tBase - 0x1000\r
+ pdeBase = pdptBase - len(PDE)\r
+ PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)\r
+ PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)\r
+ return PDE + PDPT + PML4T\r
+\r
+ def AlignAndAddPageTables():\r
+ d = open(sys.argv[1], 'rb').read()\r
+ code = NopAlign4k(d)\r
+ topAddress = 0x100000000 - len(code)\r
+ d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code\r
+ f = open(sys.argv[1], 'wb')\r
+ f.write(d)\r
+ f.close()\r
+\r
+ AlignAndAddPageTables()\r
+\r
--- /dev/null
+/** @file\r
+ Provide FSP API related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __FSP_API_LIB_H__\r
+#define __FSP_API_LIB_H__\r
+\r
+#include <FspApi.h>\r
+#include <FspInfoHeader.h>\r
+\r
+/**\r
+ Find FSP header pointer.\r
+\r
+ @param[in] FlashFvFspBase Flash address of FSP FV.\r
+\r
+ @return FSP header pointer.\r
+**/\r
+FSP_INFO_HEADER *\r
+EFIAPI\r
+FspFindFspHeader (\r
+ IN EFI_PHYSICAL_ADDRESS FlashFvFspBase\r
+ );\r
+\r
+/**\r
+ Call FSP API - FspInit.\r
+\r
+ @param[in] FspHeader FSP header pointer.\r
+ @param[in] FspInitParams Address pointer to the FSP_INIT_PARAMS structure.\r
+\r
+ @return FSP status returned by FspInit API.\r
+**/\r
+FSP_STATUS\r
+EFIAPI\r
+CallFspInit (\r
+ IN FSP_INFO_HEADER *FspHeader,\r
+ IN FSP_INIT_PARAMS *FspInitParams\r
+ );\r
+\r
+/**\r
+ Call FSP API - FspNotifyPhase.\r
+\r
+ @param[in] FspHeader FSP header pointer.\r
+ @param[in] NotifyPhaseParams Address pointer to the NOTIFY_PHASE_PARAMS structure.\r
+\r
+ @return FSP status returned by FspNotifyPhase API.\r
+**/\r
+FSP_STATUS\r
+EFIAPI\r
+CallFspNotifyPhase (\r
+ IN FSP_INFO_HEADER *FspHeader,\r
+ IN NOTIFY_PHASE_PARAMS *NotifyPhaseParams\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Provide FSP hob process related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __FSP_HOB_PROCESS_LIB_H__\r
+#define __FSP_HOB_PROCESS_LIB_H__\r
+\r
+/**\r
+ BIOS process FspBobList.\r
+\r
+ @param[in] FspHobList Pointer to the HOB data structure produced by FSP.\r
+\r
+ @return If platform process the FSP hob list successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspHobProcess (\r
+ IN VOID *FspHobList\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Provide FSP platform information related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __FSP_PLATFORM_INFO_LIB_H__\r
+#define __FSP_PLATFORM_INFO_LIB_H__\r
+\r
+/**\r
+ Get current boot mode.\r
+\r
+ @note At this point, memory is ready, PeiServices are NOT available to use.\r
+ Platform can get some data from chipset register.\r
+\r
+ @return BootMode current boot mode.\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetBootMode (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Get NVS buffer parameter.\r
+\r
+ @note At this point, memory is NOT ready, PeiServices are available to use.\r
+\r
+ @return NvsBuffer NVS buffer parameter.\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetNvsBuffer (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Get UPD region size.\r
+\r
+ @note At this point, memory is NOT ready, PeiServices are available to use.\r
+\r
+ @return UPD region size.\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetUpdRegionSize (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function overrides the default configurations in the UPD data region.\r
+\r
+ @param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strcture.\r
+\r
+ @return FspUpdRgnPtr A pointer to the UPD data region data strcture.\r
+**/\r
+VOID *\r
+EFIAPI\r
+UpdateFspUpdConfigs (\r
+ IN OUT VOID *FspUpdRgnPtr\r
+ );\r
+\r
+/**\r
+ Get S3 PEI memory information.\r
+\r
+ @note At this point, memory is ready, and PeiServices are available to use.\r
+ Platform can get some data from SMRAM directly.\r
+\r
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.\r
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.\r
+\r
+ @return If S3 PEI memory information is got successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetS3MemoryInfo (\r
+ OUT UINT64 *S3PeiMemSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase\r
+ );\r
+\r
+/**\r
+ Get stack information according to boot mode.\r
+\r
+ @note If BootMode is BOOT_ON_S3_RESUME or BOOT_ON_FLASH_UPDATE,\r
+ this stack should be in some reserved memory space.\r
+\r
+ @note If FspInitDone is TRUE, memory is ready, but no PeiServices there.\r
+ Platform can get some data from SMRAM directly.\r
+ @note If FspInitDone is FALSE, memory is NOT ready, but PeiServices are available to use.\r
+ Platform can get some data from variable via VariablePpi.\r
+\r
+ @param[in] BootMode Current boot mode.\r
+ @param[in] FspInitDone If FspInit is called.\r
+ @param[out] StackSize Stack size to be used in PEI phase.\r
+ @param[out] StackBase Stack base to be used in PEI phase.\r
+\r
+ @return If Stack information is got successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetStackInfo (\r
+ IN UINT32 BootMode,\r
+ IN BOOLEAN FspInitDone,\r
+ OUT UINT64 *StackSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *StackBase\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Provide FSP wrapper platform sec related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __FSP_PLATFORM_SEC_LIB_H__\r
+#define __FSP_PLATFORM_SEC_LIB_H__\r
+\r
+/**\r
+ A developer supplied function to perform platform specific operations.\r
+\r
+ It's a developer supplied function to perform any operations appropriate to a\r
+ given platform. It's invoked just before passing control to PEI core by SEC\r
+ core. Platform developer may modify the SecCoreData passed to PEI Core.\r
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.\r
+ The Generic SEC core module will merge this list to join the final list passed to\r
+ PEI core.\r
+\r
+ @param[in,out] SecCoreData The same parameter as passing to PEI core. It\r
+ could be overridden by this function.\r
+\r
+ @return The platform specific PPI list to be passed to PEI core or\r
+ NULL if there is no need of such platform specific PPI list.\r
+\r
+**/\r
+EFI_PEI_PPI_DESCRIPTOR *\r
+EFIAPI\r
+SecPlatformMain (\r
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData\r
+ );\r
+\r
+/**\r
+ Call PEI core entry point with new temporary RAM.\r
+\r
+ @param[in] FspHobList HobList produced by FSP.\r
+ @param[in] StartOfRange Start of temporary RAM.\r
+ @param[in] EndOfRange End of temporary RAM.\r
+**/\r
+VOID\r
+EFIAPI\r
+CallPeiCoreEntryPoint (\r
+ IN VOID *FspHobList,\r
+ IN VOID *StartOfRange,\r
+ IN VOID *EndOfRange\r
+ );\r
+\r
+/**\r
+ Save SEC context before call FspInit.\r
+\r
+ @param[in] PeiServices Pointer to PEI Services Table.\r
+**/\r
+VOID\r
+EFIAPI\r
+SaveSecContext (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Provides the services to return FSP hob list.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FSP_INIT_DONE_H_\r
+#define _FSP_INIT_DONE_H_\r
+\r
+typedef struct _FSP_INIT_DONE_PPI FSP_INIT_DONE_PPI;\r
+\r
+/**\r
+ Return Hob list produced by FSP.\r
+\r
+ @param[in] PeiServices The pointer to the PEI Services Table.\r
+ @param[in] This The pointer to this instance of this PPI.\r
+ @param[out] FspHobList The pointer to Hob list produced by FSP.\r
+\r
+ @return EFI_SUCCESS FReturn Hob list produced by FSP successfully.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *FSP_INIT_DONE_GET_FSP_HOB_LIST)(\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN FSP_INIT_DONE_PPI *This,\r
+ OUT VOID **FspHobList\r
+ );\r
+\r
+struct _FSP_INIT_DONE_PPI {\r
+ FSP_INIT_DONE_GET_FSP_HOB_LIST GetFspHobList;\r
+};\r
+\r
+extern EFI_GUID gFspInitDonePpiGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Provides the pointer to top of temporary ram.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _TOP_OF_TEMPORARY_RAM_H_\r
+#define _TOP_OF_TEMPORARY_RAM_H_\r
+\r
+extern EFI_GUID gTopOfTemporaryRamPpiGuid;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+#\r
+# Provides drivers and definitions to support fsp in EDKII bios.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = IntelFspWrapperPkg\r
+ PACKAGE_GUID = 99101BB6-6DE1-4537-85A3-FD6B594F7468\r
+ PACKAGE_VERSION = 0.1\r
+\r
+[Includes]\r
+ Include\r
+\r
+[LibraryClasses]\r
+\r
+[Guids]\r
+ #\r
+ # GUID defined in package\r
+ #\r
+ gFspWrapperTokenSpaceGuid = {0x2bc1c74a, 0x122f, 0x40b2, { 0xb2, 0x23, 0x8, 0x2b, 0x74, 0x65, 0x22, 0x5d } }\r
+\r
+ # Guid define in FSP EAS\r
+ gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
+ gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
+ gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
+ gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
+\r
+[Ppis]\r
+ gFspInitDonePpiGuid = { 0xf5ef05e4, 0xd538, 0x4774, 0x8f, 0x1b, 0xe9, 0x77, 0x30, 0x11, 0xe0, 0x38 }\r
+ gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b }\r
+\r
+[Protocols]\r
+\r
+################################################################################\r
+#\r
+# PCD Declarations section - list of all PCDs Declared by this Package\r
+# Only this package should be providing the\r
+# declaration, other packages should not.\r
+#\r
+################################################################################\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+ ## Provides the memory mapped base address of the BIOS CodeCache Flash Device.\r
+ gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001\r
+ ## Provides the size of the BIOS Flash Device.\r
+ gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
+\r
+ ## Indicates the base address of the FSP binary.\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003\r
+ ## Provides the size of the FSP binary.\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004\r
+\r
+ ## Indicates the base address of the first Microcode Patch in the Microcode Region\r
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
+ ## Indicates the offset of the Cpu Microcode.\r
+ gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x90|UINT32|0x10000007\r
+\r
+ ##\r
+ # Maximum number of Ppi is provided by SecCore.\r
+ ##\r
+ gFspWrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported|0x6|UINT32|0x20000001\r
+\r
+ # This is MAX UPD region size\r
+ gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize|0x200|UINT32|0x30000001\r
+\r
+ ## Stack size in the temporary RAM.\r
+ # 0 means half of TemporaryRamSize.\r
+ gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x40000001\r
+\r
+ # This is temporary DRAM base and size for StackTop in FspInit\r
+ gFspWrapperTokenSpaceGuid.PcdTemporaryRamBase|0x00080000|UINT32|0x40000002\r
+ gFspWrapperTokenSpaceGuid.PcdTemporaryRamSize|0x00010000|UINT32|0x40000003\r
+\r
+ ## Indicate the PEI memory size platform want to report\r
+ gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
+ ## Indicate the PEI memory size platform want to report\r
+ gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
--- /dev/null
+## @file\r
+#\r
+# Provides drivers and definitions to support fsp in EDKII bios.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ PLATFORM_NAME = IntelFspWrapperPkg\r
+ PLATFORM_GUID = BC1EC7D4-8550-4a64-B7F5-8E0EF864FFA2\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/IntelFspWrapperPkg\r
+ SUPPORTED_ARCHITECTURES = IA32|X64\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+\r
+[LibraryClasses]\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+\r
+ # Dummy - test build only\r
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf\r
+\r
+ # MdeModulePkg\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+\r
+ # UefiCpuPkg\r
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf\r
+ LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf\r
+\r
+ # FSP lib\r
+ FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf\r
+\r
+ # FSP platform sample\r
+ FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSample/BaseFspPlatformInfoLibSample.inf\r
+ FspPlatformSecLib|IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecPeiFspPlatformSecLibSample.inf\r
+ FspHobProcessLib|IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/PeiFspHobProcessLibSample.inf\r
+\r
+[LibraryClasses.common.PEIM,LibraryClasses.common.PEI_CORE]\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf\r
+\r
+[Components.Ia32]\r
+ IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf\r
+ IntelFspWrapperPkg/FspInitPei/FspInitPei.inf\r
+\r
+[Components.IA32, Components.X64]\r
+ IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
--- /dev/null
+## @file\r
+# Provide FSP API related function.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseFspApiLib\r
+ FILE_GUID = 6E4CB8C5-6144-4ae3-BA52-B6AFBCB2B2F5\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = FspApiLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+ FspApiLib.c\r
+\r
+[Sources.IA32]\r
+ IA32/DispatchExecute.c\r
+\r
+[Sources.X64]\r
+ X64/DispatchExecute.c\r
+ X64/Thunk64To32.asm\r
+ X64/Thunk64To32.S\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+\r
+[Guids]\r
+ gFspHeaderFileGuid\r
--- /dev/null
+/** @file\r
+ Provide FSP API related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Guid/FspHeaderFile.h>\r
+\r
+#include <Library/FspApiLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+/**\r
+ Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r
+ long mode.\r
+\r
+ @param[in] Function The 32bit code entry to be executed.\r
+ @param[in] Param1 The first parameter to pass to 32bit code.\r
+\r
+ @return FSP_STATUS.\r
+**/\r
+FSP_STATUS\r
+Execute32BitCode (\r
+ IN UINT64 Function,\r
+ IN UINT64 Param1\r
+ );\r
+\r
+/**\r
+ Find FSP header pointer.\r
+\r
+ @param[in] FlashFvFspBase Flash address of FSP FV.\r
+\r
+ @return FSP header pointer.\r
+**/\r
+FSP_INFO_HEADER *\r
+EFIAPI\r
+FspFindFspHeader (\r
+ IN EFI_PHYSICAL_ADDRESS FlashFvFspBase\r
+ )\r
+{\r
+ UINT8 *CheckPointer;\r
+\r
+ CheckPointer = (UINT8 *) (UINTN) FlashFvFspBase;\r
+\r
+ if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->Signature != EFI_FVH_SIGNATURE) {\r
+ return NULL;\r
+ }\r
+\r
+ if (((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset != 0) {\r
+ CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->ExtHeaderOffset;\r
+ CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)CheckPointer)->ExtHeaderSize;\r
+ CheckPointer = (UINT8 *) ALIGN_POINTER (CheckPointer, 8);\r
+ } else {\r
+ CheckPointer = CheckPointer + ((EFI_FIRMWARE_VOLUME_HEADER *)CheckPointer)->HeaderLength;\r
+ }\r
+\r
+ if (!CompareGuid (&((EFI_FFS_FILE_HEADER *)CheckPointer)->Name, &gFspHeaderFileGuid)) {\r
+ return NULL;\r
+ }\r
+\r
+ CheckPointer = CheckPointer + sizeof (EFI_FFS_FILE_HEADER);\r
+\r
+ if (((EFI_RAW_SECTION *)CheckPointer)->Type != EFI_SECTION_RAW) {\r
+ return NULL;\r
+ }\r
+\r
+ CheckPointer = CheckPointer + sizeof (EFI_RAW_SECTION);\r
+\r
+ return (FSP_INFO_HEADER *)CheckPointer;\r
+}\r
+\r
+/**\r
+ Call FSP API - FspInit.\r
+\r
+ @param[in] FspHeader FSP header pointer.\r
+ @param[in] FspInitParams Address pointer to the FSP_INIT_PARAMS structure.\r
+\r
+ @return FSP status returned by FspInit API.\r
+**/\r
+FSP_STATUS\r
+EFIAPI\r
+CallFspInit (\r
+ IN FSP_INFO_HEADER *FspHeader,\r
+ IN FSP_INIT_PARAMS *FspInitParams\r
+ )\r
+{\r
+ FSP_FSP_INIT FspInitApi;\r
+ FSP_STATUS FspStatus;\r
+\r
+ FspInitApi = (FSP_FSP_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspInitEntryOffset);\r
+ FspStatus = Execute32BitCode ((UINTN)FspInitApi, (UINTN)FspInitParams);\r
+\r
+ return FspStatus;\r
+}\r
+\r
+/**\r
+ Call FSP API - FspNotifyPhase.\r
+\r
+ @param[in] FspHeader FSP header pointer.\r
+ @param[in] NotifyPhaseParams Address pointer to the NOTIFY_PHASE_PARAMS structure.\r
+\r
+ @return FSP status returned by FspNotifyPhase API.\r
+**/\r
+FSP_STATUS\r
+EFIAPI\r
+CallFspNotifyPhase (\r
+ IN FSP_INFO_HEADER *FspHeader,\r
+ IN NOTIFY_PHASE_PARAMS *NotifyPhaseParams\r
+ )\r
+{\r
+ FSP_NOTFY_PHASE NotifyPhaseApi;\r
+ FSP_STATUS FspStatus;\r
+\r
+ NotifyPhaseApi = (FSP_NOTFY_PHASE)(UINTN)(FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);\r
+ FspStatus = Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams);\r
+\r
+ return FspStatus;\r
+}\r
--- /dev/null
+/** @file\r
+ Execute 32-bit code in Protected Mode.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <FspApi.h>\r
+\r
+typedef\r
+FSP_STATUS\r
+(FSPAPI *FSP_FUNCTION) (\r
+ IN VOID *Param1\r
+ );\r
+\r
+/**\r
+ Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r
+ long mode.\r
+\r
+ @param[in] Function The 32bit code entry to be executed.\r
+ @param[in] Param1 The first parameter to pass to 32bit code.\r
+\r
+ @return FSP_STATUS.\r
+**/\r
+FSP_STATUS\r
+Execute32BitCode (\r
+ IN UINT64 Function,\r
+ IN UINT64 Param1\r
+ )\r
+{\r
+ FSP_FUNCTION EntryFunc;\r
+ FSP_STATUS Status;\r
+\r
+ EntryFunc = (FSP_FUNCTION) (UINTN) (Function);\r
+ Status = EntryFunc ((VOID *)(UINTN)Param1);\r
+\r
+ return Status;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Execute 32-bit code in Long Mode.\r
+ Provide a thunk function to transition from long mode to compatibility mode to execute 32-bit code and then transit\r
+ back to long mode.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/BaseLib.h>\r
+#include <FspApi.h>\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow : 16;\r
+ UINT32 BaseLow : 16;\r
+ UINT32 BaseMid : 8;\r
+ UINT32 Type : 4;\r
+ UINT32 System : 1;\r
+ UINT32 Dpl : 2;\r
+ UINT32 Present : 1;\r
+ UINT32 LimitHigh : 4;\r
+ UINT32 Software : 1;\r
+ UINT32 Reserved : 1;\r
+ UINT32 DefaultSize : 1;\r
+ UINT32 Granularity : 1;\r
+ UINT32 BaseHigh : 8;\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_GDT;\r
+#pragma pack()\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {\r
+ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, /* 0x0: reserve */\r
+ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, /* 0x8: compatibility mode */\r
+ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}}, /* 0x10: for long mode */\r
+ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, /* 0x18: data */\r
+ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, /* 0x20: reserve */\r
+};\r
+\r
+//\r
+// IA32 Gdt register\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR mGdt = {\r
+ sizeof (mGdtEntries) - 1,\r
+ (UINTN) mGdtEntries\r
+ };\r
+\r
+/**\r
+ Assembly function to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r
+ long mode.\r
+\r
+ @param[in] Function The 32bit code entry to be executed.\r
+ @param[in] Param1 The first parameter to pass to 32bit code\r
+ @param[in] Param2 The second parameter to pass to 32bit code\r
+ @param[in] InternalGdtr The GDT and GDT descriptor used by this library\r
+\r
+ @return status.\r
+**/\r
+UINT32\r
+AsmExecute32BitCode (\r
+ IN UINT64 Function,\r
+ IN UINT64 Param1,\r
+ IN UINT64 Param2,\r
+ IN IA32_DESCRIPTOR *InternalGdtr\r
+ );\r
+\r
+/**\r
+ Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to\r
+ long mode.\r
+\r
+ @param[in] Function The 32bit code entry to be executed.\r
+ @param[in] Param1 The first parameter to pass to 32bit code.\r
+\r
+ @return FSP_STATUS.\r
+**/\r
+FSP_STATUS\r
+Execute32BitCode (\r
+ IN UINT64 Function,\r
+ IN UINT64 Param1\r
+ )\r
+{\r
+ return AsmExecute32BitCode (Function, Param1, 0, &mGdt);\r
+}\r
+\r
--- /dev/null
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+# Module Name:\r
+#\r
+# Thunk64To32.asm\r
+#\r
+# Abstract:\r
+#\r
+# This is the assembly code to transition from long mode to compatibility mode to execute 32-bit code and then\r
+# transit back to long mode.\r
+#\r
+#-------------------------------------------------------------------------------\r
+\r
+#----------------------------------------------------------------------------\r
+# Procedure: AsmExecute32BitCode\r
+#\r
+# Input: None\r
+#\r
+# Output: None\r
+#\r
+# Prototype: UINT32\r
+# AsmExecute32BitCode (\r
+# IN UINT64 Function,\r
+# IN UINT64 Param1,\r
+# IN UINT64 Param2,\r
+# IN IA32_DESCRIPTOR *InternalGdtr\r
+# );\r
+#\r
+#\r
+# Description: A thunk function to execute 32-bit code in long mode.\r
+#\r
+#----------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(AsmExecute32BitCode)\r
+ASM_PFX(AsmExecute32BitCode):\r
+ #\r
+ # save IFLAG and disable it\r
+ #\r
+ pushfq\r
+ cli\r
+\r
+ #\r
+ # save orignal GDTR and CS\r
+ #\r
+ movl %ds, %eax\r
+ push %rax\r
+ movl %cs, %eax\r
+ push %rax\r
+ subq $0x10, %rsp\r
+ sgdt (%rsp)\r
+ #\r
+ # load internal GDT\r
+ #\r
+ lgdt (%r9)\r
+ #\r
+ # Save general purpose register and rflag register\r
+ #\r
+ pushfq\r
+ push %rdi\r
+ push %rsi\r
+ push %rbp\r
+ push %rbx\r
+\r
+ #\r
+ # save CR3\r
+ #\r
+ movq %cr3, %rax\r
+ movq %rax, %rbp\r
+\r
+ #\r
+ # Prepare the CS and return address for the transition from 32-bit to 64-bit mode\r
+ #\r
+ movq $0x10, %rax # load long mode selector\r
+ shl $32, %rax\r
+ lea ReloadCS(%rip), %r9 #Assume the ReloadCS is under 4G\r
+ orq %r9, %rax\r
+ push %rax\r
+ #\r
+ # Save parameters for 32-bit function call\r
+ #\r
+ movq %r8, %rax\r
+ shl $32, %rax\r
+ orq %rdx, %rax\r
+ push %rax\r
+ #\r
+ # save the 32-bit function entry and the return address into stack which will be\r
+ # retrieve in compatibility mode.\r
+ #\r
+ lea ReturnBack(%rip), %rax #Assume the ReloadCS is under 4G\r
+ shl $32, %rax\r
+ orq %rcx, %rax\r
+ push %rax\r
+\r
+ #\r
+ # let rax save DS\r
+ #\r
+ movq $0x18, %rax\r
+\r
+ #\r
+ # Change to Compatible Segment\r
+ #\r
+ movq $8, %rcx # load compatible mode selector\r
+ shl $32, %rcx\r
+ lea Compatible(%rip), %rdx # assume address < 4G\r
+ orq %rdx, %rcx\r
+ push %rcx\r
+ .byte 0xcb # retf\r
+\r
+Compatible:\r
+ # reload DS/ES/SS to make sure they are correct referred to current GDT\r
+ movw %ax, %ds\r
+ movw %ax, %es\r
+ movw %ax, %ss\r
+\r
+ #\r
+ # Disable paging\r
+ #\r
+ movq %cr0, %rcx\r
+ btc $31, %ecx\r
+ movq %rcx, %cr0\r
+ #\r
+ # Clear EFER.LME\r
+ #\r
+ movl $0xC0000080, %ecx\r
+ rdmsr\r
+ btc $8, %eax\r
+ wrmsr\r
+\r
+# Now we are in protected mode\r
+ #\r
+ # Call 32-bit function. Assume the function entry address and parameter value is less than 4G\r
+ #\r
+ pop %rax # Here is the function entry\r
+ #\r
+ # Now the parameter is at the bottom of the stack, then call in to IA32 function.\r
+ #\r
+ jmp *%rax\r
+ReturnBack:\r
+ movl %eax, %ebx # save return status\r
+ pop %rcx # drop param1\r
+ pop %rcx # drop param2\r
+\r
+ #\r
+ # restore CR4\r
+ #\r
+ movq %cr4, %rax\r
+ bts $5, %eax\r
+ movq %rax, %cr4\r
+\r
+ #\r
+ # restore CR3\r
+ #\r
+ movl %ebp, %eax\r
+ movq %rax, %cr3\r
+\r
+ #\r
+ # Set EFER.LME to re-enable ia32-e\r
+ #\r
+ movl $0xC0000080, %ecx\r
+ rdmsr\r
+ bts $8, %eax\r
+ wrmsr\r
+ #\r
+ # Enable paging\r
+ #\r
+ movq %cr0, %rax\r
+ bts $31, %eax\r
+ mov %rax, %cr0\r
+# Now we are in compatible mode\r
+\r
+ #\r
+ # Reload cs register\r
+ #\r
+ .byte 0xcb # retf\r
+ReloadCS:\r
+ #\r
+ # Now we're in Long Mode\r
+ #\r
+ #\r
+ # Restore C register and eax hold the return status from 32-bit function.\r
+ # Note: Do not touch rax from now which hold the return value from IA32 function\r
+ #\r
+ movl %ebx, %eax # put return status to EAX\r
+ pop %rbx\r
+ pop %rbp\r
+ pop %rsi\r
+ pop %rdi\r
+ popfq\r
+ #\r
+ # Switch to orignal GDT and CS. here rsp is pointer to the orignal GDT descriptor.\r
+ #\r
+ lgdt (%rsp)\r
+ #\r
+ # drop GDT descriptor in stack\r
+ #\r
+ addq $0x10, %rsp\r
+ #\r
+ # switch to orignal CS and GDTR\r
+ #\r
+ pop %r9 # get CS\r
+ shl $32, %r9 # rcx[32..47] <- Cs\r
+ lea ReturnToLongMode(%rip), %rcx\r
+ orq %r9, %rcx\r
+ push %rcx\r
+ .byte 0xcb # retf\r
+ReturnToLongMode:\r
+ #\r
+ # Reload original DS/ES/SS\r
+ #\r
+ pop %rcx\r
+ movl %ecx, %ds\r
+ movl %ecx, %es\r
+ movl %ecx, %ss\r
+\r
+ #\r
+ # Restore IFLAG\r
+ #\r
+ popfq\r
+\r
+ ret\r
+\r
--- /dev/null
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;\r
+; Module Name:\r
+;\r
+; Thunk64To32.asm\r
+;\r
+; Abstract:\r
+;\r
+; This is the assembly code to transition from long mode to compatibility mode to execute 32-bit code and then\r
+; transit back to long mode.\r
+;\r
+;-------------------------------------------------------------------------------\r
+ .code\r
+;----------------------------------------------------------------------------\r
+; Procedure: AsmExecute32BitCode\r
+;\r
+; Input: None\r
+;\r
+; Output: None\r
+;\r
+; Prototype: UINT32\r
+; AsmExecute32BitCode (\r
+; IN UINT64 Function,\r
+; IN UINT64 Param1,\r
+; IN UINT64 Param2,\r
+; IN IA32_DESCRIPTOR *InternalGdtr\r
+; );\r
+;\r
+;\r
+; Description: A thunk function to execute 32-bit code in long mode.\r
+;\r
+;----------------------------------------------------------------------------\r
+AsmExecute32BitCode PROC\r
+ ;\r
+ ; save IFLAG and disable it\r
+ ;\r
+ pushfq\r
+ cli\r
+\r
+ ;\r
+ ; save orignal GDTR and CS\r
+ ;\r
+ mov rax, ds\r
+ push rax\r
+ mov rax, cs\r
+ push rax\r
+ sub rsp, 10h\r
+ sgdt fword ptr [rsp]\r
+ ;\r
+ ; load internal GDT\r
+ ;\r
+ lgdt fword ptr [r9]\r
+ ;\r
+ ; Save general purpose register and rflag register\r
+ ;\r
+ pushfq\r
+ push rdi\r
+ push rsi\r
+ push rbp\r
+ push rbx\r
+\r
+ ;\r
+ ; save CR3\r
+ ;\r
+ mov rax, cr3\r
+ mov rbp, rax\r
+\r
+ ;\r
+ ; Prepare the CS and return address for the transition from 32-bit to 64-bit mode\r
+ ;\r
+ mov rax, 10h ; load long mode selector\r
+ shl rax, 32\r
+ mov r9, OFFSET ReloadCS ;Assume the ReloadCS is under 4G\r
+ or rax, r9\r
+ push rax\r
+ ;\r
+ ; Save parameters for 32-bit function call\r
+ ;\r
+ mov rax, r8\r
+ shl rax, 32\r
+ or rax, rdx\r
+ push rax\r
+ ;\r
+ ; save the 32-bit function entry and the return address into stack which will be\r
+ ; retrieve in compatibility mode.\r
+ ;\r
+ mov rax, OFFSET ReturnBack ;Assume the ReloadCS is under 4G\r
+ shl rax, 32\r
+ or rax, rcx\r
+ push rax\r
+\r
+ ;\r
+ ; let rax save DS\r
+ ;\r
+ mov rax, 018h\r
+\r
+ ;\r
+ ; Change to Compatible Segment\r
+ ;\r
+ mov rcx, 08h ; load compatible mode selector\r
+ shl rcx, 32\r
+ mov rdx, OFFSET Compatible ; assume address < 4G\r
+ or rcx, rdx\r
+ push rcx\r
+ retf\r
+\r
+Compatible:\r
+ ; reload DS/ES/SS to make sure they are correct referred to current GDT\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov ss, ax\r
+\r
+ ;\r
+ ; Disable paging\r
+ ;\r
+ mov rcx, cr0\r
+ btc ecx, 31\r
+ mov cr0, rcx\r
+ ;\r
+ ; Clear EFER.LME\r
+ ;\r
+ mov ecx, 0C0000080h\r
+ rdmsr\r
+ btc eax, 8\r
+ wrmsr\r
+\r
+; Now we are in protected mode\r
+ ;\r
+ ; Call 32-bit function. Assume the function entry address and parameter value is less than 4G\r
+ ;\r
+ pop rax ; Here is the function entry\r
+ ;\r
+ ; Now the parameter is at the bottom of the stack, then call in to IA32 function.\r
+ ;\r
+ jmp rax\r
+ReturnBack:\r
+ mov ebx, eax ; save return status\r
+ pop rcx ; drop param1\r
+ pop rcx ; drop param2\r
+\r
+ ;\r
+ ; restore CR4\r
+ ;\r
+ mov rax, cr4\r
+ bts eax, 5\r
+ mov cr4, rax\r
+\r
+ ;\r
+ ; restore CR3\r
+ ;\r
+ mov eax, ebp\r
+ mov cr3, rax\r
+\r
+ ;\r
+ ; Set EFER.LME to re-enable ia32-e\r
+ ;\r
+ mov ecx, 0C0000080h\r
+ rdmsr\r
+ bts eax, 8\r
+ wrmsr\r
+ ;\r
+ ; Enable paging\r
+ ;\r
+ mov rax, cr0\r
+ bts eax, 31\r
+ mov cr0, rax\r
+; Now we are in compatible mode\r
+\r
+ ;\r
+ ; Reload cs register\r
+ ;\r
+ retf\r
+ReloadCS:\r
+ ;\r
+ ; Now we're in Long Mode\r
+ ;\r
+ ;\r
+ ; Restore C register and eax hold the return status from 32-bit function.\r
+ ; Note: Do not touch rax from now which hold the return value from IA32 function\r
+ ;\r
+ mov eax, ebx ; put return status to EAX\r
+ pop rbx\r
+ pop rbp\r
+ pop rsi\r
+ pop rdi\r
+ popfq\r
+ ;\r
+ ; Switch to orignal GDT and CS. here rsp is pointer to the orignal GDT descriptor.\r
+ ;\r
+ lgdt fword ptr[rsp]\r
+ ;\r
+ ; drop GDT descriptor in stack\r
+ ;\r
+ add rsp, 10h\r
+ ;\r
+ ; switch to orignal CS and GDTR\r
+ ;\r
+ pop r9 ; get CS\r
+ shl r9, 32 ; rcx[32..47] <- Cs\r
+ mov rcx, OFFSET @F\r
+ or rcx, r9\r
+ push rcx\r
+ retf\r
+@@:\r
+ ;\r
+ ; Reload original DS/ES/SS\r
+ ;\r
+ pop rcx\r
+ mov ds, rcx\r
+ mov es, rcx\r
+ mov ss, rcx\r
+\r
+ ;\r
+ ; Restore IFLAG\r
+ ;\r
+ popfq\r
+\r
+ ret\r
+AsmExecute32BitCode ENDP\r
+\r
+ END\r
--- /dev/null
+## @file\r
+# Sample to provide FSP platform information related function.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseFspPlatformInfoLibSample\r
+ FILE_GUID = 24C6F3E2-6ACD-436b-A604-56A5CF742A55\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = FspPlatformInfoLib\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+ FspPlatformInfoLibSample.c\r
+\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+\r
+[Pcd]\r
+ gFspWrapperTokenSpaceGuid.PcdTemporaryRamBase\r
+ gFspWrapperTokenSpaceGuid.PcdTemporaryRamSize\r
--- /dev/null
+/** @file\r
+ Sample to provide FSP platform information related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/PcdLib.h>\r
+\r
+/**\r
+ Get current boot mode.\r
+\r
+ @note At this point, memory is ready, PeiServices are NOT available to use.\r
+ Platform can get some data from chipset register.\r
+\r
+ @return BootMode current boot mode.\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ Get NVS buffer parameter.\r
+\r
+ @note At this point, memory is NOT ready, PeiServices are available to use.\r
+\r
+ @return NvsBuffer NVS buffer parameter.\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetNvsBuffer (\r
+ VOID\r
+ )\r
+{\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Get UPD region size.\r
+\r
+ @note At this point, memory is NOT ready, PeiServices are available to use.\r
+\r
+ @return UPD region size.\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetUpdRegionSize (\r
+ VOID\r
+ )\r
+{\r
+ return 0;\r
+}\r
+\r
+/**\r
+ This function overrides the default configurations in the UPD data region.\r
+\r
+ @note At this point, memory is NOT ready, PeiServices are available to use.\r
+\r
+ @param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strcture.\r
+\r
+ @return FspUpdRgnPtr A pointer to the UPD data region data strcture.\r
+**/\r
+VOID *\r
+EFIAPI\r
+UpdateFspUpdConfigs (\r
+ IN OUT VOID *FspUpdRgnPtr\r
+ )\r
+{\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Get S3 PEI memory information.\r
+\r
+ @note At this point, memory is ready, and PeiServices are available to use.\r
+ Platform can get some data from SMRAM directly.\r
+\r
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.\r
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.\r
+\r
+ @return If S3 PEI memory information is got successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetS3MemoryInfo (\r
+ OUT UINT64 *S3PeiMemSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ Get stack information according to boot mode.\r
+\r
+ @note If BootMode is BOOT_ON_S3_RESUME or BOOT_ON_FLASH_UPDATE,\r
+ this stack should be in some reserved memory space.\r
+\r
+ @note If FspInitDone is TRUE, memory is ready, but no PeiServices there.\r
+ Platform can get some data from SMRAM directly.\r
+ @note If FspInitDone is FALSE, memory is NOT ready, but PeiServices are available to use.\r
+ Platform can get some data from variable via VariablePpi.\r
+\r
+ @param[in] BootMode Current boot mode.\r
+ @param[in] FspInitDone If FspInit is called.\r
+ @param[out] StackSize Stack size to be used in PEI phase.\r
+ @param[out] StackBase Stack base to be used in PEI phase.\r
+\r
+ @return If Stack information is got successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetStackInfo (\r
+ IN UINT32 BootMode,\r
+ IN BOOLEAN FspInitDone,\r
+ OUT UINT64 *StackSize,\r
+ OUT EFI_PHYSICAL_ADDRESS *StackBase\r
+ )\r
+{\r
+ *StackBase = PcdGet32 (PcdTemporaryRamBase);\r
+ *StackSize = PcdGet32 (PcdTemporaryRamSize);\r
+\r
+ if (BootMode == BOOT_ON_S3_RESUME) {\r
+ if (!FspInitDone) {\r
+ } else {\r
+ }\r
+ } else if (BootMode == BOOT_ON_FLASH_UPDATE) {\r
+ if (!FspInitDone) {\r
+ } else {\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ Sample to provide FSP hob process related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/FspPlatformInfoLib.h>\r
+\r
+#include <Guid/GuidHobFspEas.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/Capsule.h>\r
+\r
+//\r
+// Additional pages are used by DXE memory manager.\r
+// It should be consistent between RetrieveRequiredMemorySize() and GetPeiMemSize()\r
+//\r
+#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)\r
+\r
+/**\r
+ Get the mem size in memory type infromation table.\r
+\r
+ @param[in] PeiServices PEI Services table.\r
+\r
+ @return the mem size in memory type infromation table.\r
+**/\r
+UINT64\r
+GetMemorySizeInMemoryTypeInformation (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;\r
+ UINT8 Index;\r
+ UINTN TempPageNum;\r
+\r
+ MemoryData = NULL;\r
+ Status = (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES**)PeiServices, (VOID **) &Hob.Raw);\r
+ while (!END_OF_HOB_LIST (Hob)) {\r
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&\r
+ CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)) {\r
+ MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));\r
+ break;\r
+ }\r
+\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+\r
+ if (MemoryData == NULL) {\r
+ return 0;\r
+ }\r
+\r
+ TempPageNum = 0;\r
+ for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {\r
+ //\r
+ // Accumulate default memory size requirements\r
+ //\r
+ TempPageNum += MemoryData[Index].NumberOfPages;\r
+ }\r
+\r
+ return TempPageNum * EFI_PAGE_SIZE;\r
+}\r
+\r
+/**\r
+ Get the mem size need to be reserved in PEI phase.\r
+\r
+ @param[in] PeiServices PEI Services table.\r
+\r
+ @return the mem size need to be reserved in PEI phase.\r
+**/\r
+UINT64\r
+RetrieveRequiredMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ UINT64 Size;\r
+\r
+ Size = GetMemorySizeInMemoryTypeInformation (PeiServices);\r
+ return Size + PEI_ADDITIONAL_MEMORY_SIZE;\r
+}\r
+\r
+/**\r
+ Get the mem size need to be consumed and reserved in PEI phase.\r
+\r
+ @param[in] PeiServices PEI Services table.\r
+ @param[in] BootMode Current boot mode.\r
+\r
+ @return the mem size need to be consumed and reserved in PEI phase.\r
+**/\r
+UINT64\r
+GetPeiMemSize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN UINT32 BootMode\r
+ )\r
+{\r
+ UINT64 Size;\r
+ UINT64 MinSize;\r
+\r
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ return PcdGet32 (PcdPeiRecoveryMinMemSize);\r
+ }\r
+\r
+ Size = GetMemorySizeInMemoryTypeInformation (PeiServices);\r
+\r
+ if (BootMode == BOOT_ON_FLASH_UPDATE) {\r
+ //\r
+ // Maybe more size when in CapsuleUpdate phase ?\r
+ //\r
+ MinSize = PcdGet32 (PcdPeiMinMemSize);\r
+ } else {\r
+ MinSize = PcdGet32 (PcdPeiMinMemSize);\r
+ }\r
+\r
+ return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;\r
+}\r
+\r
+/**\r
+ BIOS process FspBobList.\r
+\r
+ @param[in] FspHobList Pointer to the HOB data structure produced by FSP.\r
+\r
+ @return If platform process the FSP hob list successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspHobProcess (\r
+ IN VOID *FspHobList\r
+ )\r
+{\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ UINT64 LowMemorySize;\r
+ UINT64 FspMemorySize;\r
+ EFI_PHYSICAL_ADDRESS FspMemoryBase;\r
+ UINT64 PeiMemSize;\r
+ EFI_PHYSICAL_ADDRESS PeiMemBase;\r
+ UINT64 S3PeiMemSize;\r
+ EFI_PHYSICAL_ADDRESS S3PeiMemBase;\r
+ BOOLEAN FoundFspMemHob;\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MODE BootMode;\r
+ PEI_CAPSULE_PPI *Capsule;\r
+ VOID *CapsuleBuffer;\r
+ UINTN CapsuleBufferLength;\r
+ UINT64 RequiredMemSize;\r
+ EFI_PEI_SERVICES **PeiServices;\r
+\r
+ PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();\r
+\r
+ PeiServicesGetBootMode (&BootMode);\r
+\r
+ PeiMemBase = 0;\r
+ LowMemorySize = 0;\r
+ FspMemorySize = 0;\r
+ FspMemoryBase = 0;\r
+ FoundFspMemHob = FALSE;\r
+\r
+ //\r
+ // Parse the hob list from fsp\r
+ // Report all the resource hob except the memory between 1M and 4G\r
+ //\r
+ Hob.Raw = (UINT8 *)(UINTN)FspHobList;\r
+ DEBUG((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));\r
+\r
+ while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw)) != NULL) {\r
+ DEBUG((DEBUG_INFO, "\nResourceType: 0x%x\n", Hob.ResourceDescriptor->ResourceType));\r
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||\r
+ (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED)) {\r
+ DEBUG((DEBUG_INFO, "ResourceAttribute: 0x%x\n", Hob.ResourceDescriptor->ResourceAttribute));\r
+ DEBUG((DEBUG_INFO, "PhysicalStart: 0x%x\n", Hob.ResourceDescriptor->PhysicalStart));\r
+ DEBUG((DEBUG_INFO, "ResourceLength: 0x%x\n", Hob.ResourceDescriptor->ResourceLength));\r
+ DEBUG((DEBUG_INFO, "Owner: %g\n\n", &Hob.ResourceDescriptor->Owner));\r
+ }\r
+\r
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) // Found the low memory length below 4G\r
+ && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)\r
+ && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)) {\r
+ LowMemorySize += Hob.ResourceDescriptor->ResourceLength;\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ continue;\r
+ }\r
+\r
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) // Found the low memory length below 4G\r
+ && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)\r
+ && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)\r
+ && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobGuid))) {\r
+ FoundFspMemHob = TRUE;\r
+ FspMemoryBase = Hob.ResourceDescriptor->PhysicalStart;\r
+ FspMemorySize = Hob.ResourceDescriptor->ResourceLength;\r
+ DEBUG((DEBUG_INFO, "Find fsp mem hob, base 0x%x, len 0x%x\n", FspMemoryBase, FspMemorySize));\r
+ }\r
+\r
+ //\r
+ // Report the resource hob\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ Hob.ResourceDescriptor->ResourceType,\r
+ Hob.ResourceDescriptor->ResourceAttribute,\r
+ Hob.ResourceDescriptor->PhysicalStart,\r
+ Hob.ResourceDescriptor->ResourceLength\r
+ );\r
+\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+\r
+ if (!FoundFspMemHob) {\r
+ DEBUG((DEBUG_INFO, "Didn't find the fsp used memory information.\n"));\r
+ //ASSERT(FALSE);\r
+ }\r
+\r
+ DEBUG((DEBUG_INFO, "LowMemorySize: 0x%x.\n", LowMemorySize));\r
+ DEBUG((DEBUG_INFO, "FspMemoryBase: 0x%x.\n", FspMemoryBase));\r
+ DEBUG((DEBUG_INFO, "FspMemorySize: 0x%x.\n", FspMemorySize));\r
+\r
+ if (BootMode == BOOT_ON_S3_RESUME) {\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ // EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ BASE_1MB,\r
+ LowMemorySize\r
+ );\r
+\r
+ Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase, S3PeiMemSize));\r
+\r
+ //\r
+ // Make sure Stack and PeiMemory are not overlap - JYAO1\r
+ //\r
+\r
+ Status = PeiServicesInstallPeiMemory (\r
+ S3PeiMemBase,\r
+ S3PeiMemSize\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else {\r
+ PeiMemSize = GetPeiMemSize (PeiServices, BootMode);\r
+ DEBUG((DEBUG_INFO, "PEI memory size = %Xh bytes\n", PeiMemSize));\r
+\r
+ //\r
+ // Capsule mode\r
+ //\r
+ Capsule = NULL;\r
+ CapsuleBuffer = NULL;\r
+ CapsuleBufferLength = 0;\r
+ if (BootMode == BOOT_ON_FLASH_UPDATE) {\r
+ Status = PeiServicesLocatePpi (\r
+ &gPeiCapsulePpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &Capsule\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (Status == EFI_SUCCESS) {\r
+ //\r
+ // Make sure Stack and CapsuleBuffer are not overlap - JYAO1\r
+ //\r
+ CapsuleBuffer = (VOID *)(UINTN)BASE_1MB;\r
+ CapsuleBufferLength = (UINTN)(LowMemorySize - PeiMemSize);\r
+ //\r
+ // Call the Capsule PPI Coalesce function to coalesce the capsule data.\r
+ //\r
+ Status = Capsule->Coalesce (PeiServices, &CapsuleBuffer, &CapsuleBufferLength);\r
+ }\r
+ }\r
+\r
+ RequiredMemSize = RetrieveRequiredMemorySize (PeiServices);\r
+ DEBUG((DEBUG_INFO, "Required memory size = %Xh bytes\n", RequiredMemSize));\r
+\r
+ //\r
+ // Report the main memory\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ BASE_1MB,\r
+ LowMemorySize\r
+ );\r
+\r
+ //\r
+ // Make sure Stack and CapsuleBuffer are not overlap - JYAO1\r
+ //\r
+\r
+ //\r
+ // Install efi memory\r
+ //\r
+ PeiMemBase = BASE_1MB + LowMemorySize - PeiMemSize;\r
+ Status = PeiServicesInstallPeiMemory (\r
+ PeiMemBase,\r
+ PeiMemSize - RequiredMemSize\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (Capsule != NULL) {\r
+ Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength);\r
+ }\r
+ }\r
+\r
+ //\r
+ // NV Storage Hob\r
+ //\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Sample to provide FSP hob process related function.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PeiFspHobProcessLibSample\r
+ FILE_GUID = C7B7070B-E5A8-4b86-9110-BDCA1095F496\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = FspHobProcessLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+ FspHobProcessLibSample.c\r
+\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ HobLib\r
+ DebugLib\r
+ FspPlatformInfoLib\r
+ PeiServicesLib\r
+ PeiServicesTablePointerLib\r
+\r
+[Pcd]\r
+ gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize\r
+ gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize\r
+\r
+[Guids]\r
+ gFspReservedMemoryResourceHobGuid\r
+ gEfiMemoryTypeInformationGuid\r
+\r
+[Ppis]\r
+ gPeiCapsulePpiGuid\r
--- /dev/null
+/** @file\r
+ Sample to provide FSP wrapper platform sec related function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/SecPerformance.h>\r
+#include <Ppi/TemporaryRamSupport.h>\r
+\r
+#include <Library/LocalApicLib.h>\r
+\r
+/**\r
+ This interface conveys state information out of the Security (SEC) phase into PEI.\r
+\r
+ @param[in] PeiServices Pointer to the PEI Services Table.\r
+ @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.\r
+ @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPlatformInformation (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN OUT UINT64 *StructureSize,\r
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
+ );\r
+\r
+/**\r
+ This interface conveys performance information out of the Security (SEC) phase into PEI.\r
+\r
+ This service is published by the SEC phase. The SEC phase handoff has an optional\r
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the\r
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,\r
+ this information is encapsulated into the data structure abstracted by this service.\r
+ This information is collected for the boot-strap processor (BSP) on IA-32.\r
+\r
+ @param[in] PeiServices The pointer to the PEI Services Table.\r
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.\r
+ @param[out] Performance The pointer to performance data collected in SEC phase.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecGetPerformance (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_SEC_PERFORMANCE_PPI *This,\r
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance\r
+ );\r
+\r
+/**\r
+ This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+ permanent memory.\r
+\r
+ @param[in] PeiServices Pointer to the PEI Services Table.\r
+ @param[in] TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param[in] PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param[in] CopySize Amount of memory to migrate from temporary to permanent memory.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+ TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ );\r
+\r
+EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformationPpi = {\r
+ SecPlatformInformation\r
+};\r
+\r
+PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {\r
+ SecGetPerformance\r
+};\r
+\r
+EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {\r
+ SecTemporaryRamSupport\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &gEfiSecPlatformInformationPpiGuid,\r
+ &mSecPlatformInformationPpi\r
+ },\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &gPeiSecPerformancePpiGuid,\r
+ &mSecPerformancePpi\r
+ },\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gEfiTemporaryRamSupportPpiGuid,\r
+ &gSecTemporaryRamSupportPpi\r
+ },\r
+};\r
+\r
+/**\r
+ A developer supplied function to perform platform specific operations.\r
+\r
+ It's a developer supplied function to perform any operations appropriate to a\r
+ given platform. It's invoked just before passing control to PEI core by SEC\r
+ core. Platform developer may modify the SecCoreData passed to PEI Core.\r
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.\r
+ The Generic SEC core module will merge this list to join the final list passed to\r
+ PEI core.\r
+\r
+ @param[in,out] SecCoreData The same parameter as passing to PEI core. It\r
+ could be overridden by this function.\r
+\r
+ @return The platform specific PPI list to be passed to PEI core or\r
+ NULL if there is no need of such platform specific PPI list.\r
+\r
+**/\r
+EFI_PEI_PPI_DESCRIPTOR *\r
+EFIAPI\r
+SecPlatformMain (\r
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData\r
+ )\r
+{\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+\r
+ InitializeApicTimer (0, (UINT32) -1, TRUE, 5);\r
+\r
+ PpiList = &mPeiSecPlatformPpi[0];\r
+\r
+ return PpiList;\r
+}\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# AsmSaveSecContext.S\r
+#\r
+# Abstract:\r
+#\r
+# Save Sec Conext before call FspInit API\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#----------------------------------------------------------------------------\r
+# MMX Usage:\r
+# MM0 = BIST State\r
+# MM5 = Save time-stamp counter value high32bit\r
+# MM6 = Save time-stamp counter value low32bit.\r
+#\r
+# It should be same as SecEntry.asm and PeiCoreEntry.asm.\r
+#----------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(AsmSaveBistValue)\r
+ASM_PFX(AsmSaveBistValue):\r
+ movl 4(%esp), %eax\r
+ movd %eax, %mm0\r
+ ret\r
+\r
+ASM_GLOBAL ASM_PFX(AsmSaveTickerValue)\r
+ASM_PFX(AsmSaveTickerValue):\r
+ movl 4(%esp), %eax\r
+ movd %eax, %mm6\r
+ movl 8(%esp), %eax\r
+ movd %eax, %mm5\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; AsmSaveSecContext.asm\r
+;\r
+; Abstract:\r
+;\r
+; Save Sec Conext before call FspInit API\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+.686p\r
+.xmm\r
+.model flat,c\r
+.code\r
+\r
+;----------------------------------------------------------------------------\r
+; MMX Usage:\r
+; MM0 = BIST State\r
+; MM5 = Save time-stamp counter value high32bit\r
+; MM6 = Save time-stamp counter value low32bit.\r
+;\r
+; It should be same as SecEntry.asm and PeiCoreEntry.asm.\r
+;----------------------------------------------------------------------------\r
+\r
+AsmSaveBistValue PROC PUBLIC\r
+ mov eax, [esp+4]\r
+ movd mm0, eax\r
+ ret\r
+AsmSaveBistValue ENDP\r
+\r
+AsmSaveTickerValue PROC PUBLIC\r
+ mov eax, [esp+4]\r
+ movd mm6, eax\r
+ mov eax, [esp+8]\r
+ movd mm5, eax\r
+ ret\r
+AsmSaveTickerValue ENDP\r
+\r
+END\r
--- /dev/null
+/** @file\r
+ Fsp related definitions\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Fv Header\r
+//\r
+#define FVH_SIGINATURE_OFFSET 0x28\r
+#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH\r
+#define FVH_HEADER_LENGTH_OFFSET 0x30\r
+#define FVH_EXTHEADER_OFFSET_OFFSET 0x34\r
+#define FVH_EXTHEADER_SIZE_OFFSET 0x10\r
+\r
+//\r
+// Ffs Header\r
+//\r
+#define FSP_HEADER_GUID_DWORD1 0x912740BE\r
+#define FSP_HEADER_GUID_DWORD2 0x47342284\r
+#define FSP_HEADER_GUID_DWORD3 0xB08471B9\r
+#define FSP_HEADER_GUID_DWORD4 0x0C3F3527\r
+#define FFS_HEADER_SIZE_VALUE 0x18\r
+\r
+//\r
+// Section Header\r
+//\r
+#define SECTION_HEADER_TYPE_OFFSET 0x03\r
+#define RAW_SECTION_HEADER_SIZE_VALUE 0x04\r
+\r
+//\r
+// Fsp Header\r
+//\r
+#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C\r
+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# PeiCoreEntry.S\r
+#\r
+# Abstract:\r
+#\r
+# Find and call SecStartup\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)\r
+ASM_PFX(CallPeiCoreEntryPoint):\r
+ #\r
+ # Obtain the hob list pointer\r
+ #\r
+ movl 0x4(%esp), %eax\r
+ #\r
+ # Obtain the stack information\r
+ # ECX: start of range\r
+ # EDX: end of range\r
+ #\r
+ movl 0x8(%esp), %ecx\r
+ movl 0xC(%esp), %edx\r
+\r
+ #\r
+ # Platform init\r
+ #\r
+ pushal\r
+ pushl %edx\r
+ pushl %ecx\r
+ pushl %eax\r
+ call ASM_PFX(PlatformInit)\r
+ popl %eax\r
+ popl %eax\r
+ popl %eax\r
+ popal\r
+\r
+ #\r
+ # Set stack top pointer\r
+ #\r
+ movl %edx, %esp\r
+\r
+ #\r
+ # Push the hob list pointer\r
+ #\r
+ pushl %eax\r
+\r
+ #\r
+ # Save the value\r
+ # ECX: start of range\r
+ # EDX: end of range\r
+ #\r
+ movl %esp, %ebp\r
+ pushl %ecx\r
+ pushl %edx\r
+\r
+ #\r
+ # Push processor count to stack first, then BIST status (AP then BSP)\r
+ #\r
+ movl $1, %eax\r
+ cpuid\r
+ shr $16, %ebx\r
+ andl $0x000000FF, %ebx\r
+ cmp $1, %bl\r
+ jae PushProcessorCount\r
+\r
+ #\r
+ # Some processors report 0 logical processors. Effectively 0 = 1.\r
+ # So we fix up the processor count\r
+ #\r
+ inc %ebx\r
+\r
+PushProcessorCount:\r
+ pushl %ebx\r
+\r
+ #\r
+ # We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r
+ # for all processor threads\r
+ #\r
+ xorl %ecx, %ecx\r
+ movb %bl, %cl\r
+PushBist:\r
+ movd %mm0, %eax\r
+ pushl %eax\r
+ loop PushBist\r
+\r
+ # Save Time-Stamp Counter\r
+ movd %mm5, %eax\r
+ pushl %eax\r
+\r
+ movd %mm6, %eax\r
+ pushl %eax\r
+\r
+ #\r
+ # Pass entry point of the PEI core\r
+ #\r
+ movl $0xFFFFFFE0, %edi\r
+ pushl %ds:(%edi)\r
+\r
+ #\r
+ # Pass BFV into the PEI Core\r
+ #\r
+ movl $0xFFFFFFFC, %edi\r
+ pushl %ds:(%edi)\r
+\r
+ #\r
+ # Pass stack size into the PEI Core\r
+ #\r
+ movl -4(%ebp), %ecx\r
+ movl -8(%ebp), %edx\r
+ pushl %ecx # RamBase\r
+\r
+ subl %ecx, %edx\r
+ pushl %edx # RamSize\r
+\r
+ #\r
+ # Pass Control into the PEI Core\r
+ #\r
+ call ASM_PFX(SecStartup)\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; PeiCoreEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+; Find and call SecStartup\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+.686p\r
+.xmm\r
+.model flat, c\r
+.code\r
+\r
+EXTRN SecStartup:NEAR\r
+EXTRN PlatformInit:NEAR\r
+\r
+CallPeiCoreEntryPoint PROC PUBLIC\r
+ ;\r
+ ; Obtain the hob list pointer\r
+ ;\r
+ mov eax, [esp+4]\r
+ ;\r
+ ; Obtain the stack information\r
+ ; ECX: start of range\r
+ ; EDX: end of range\r
+ ;\r
+ mov ecx, [esp+8]\r
+ mov edx, [esp+0Ch]\r
+\r
+ ;\r
+ ; Platform init\r
+ ;\r
+ pushad\r
+ push edx\r
+ push ecx\r
+ push eax\r
+ call PlatformInit\r
+ pop eax\r
+ pop eax\r
+ pop eax\r
+ popad\r
+\r
+ ;\r
+ ; Set stack top pointer\r
+ ;\r
+ mov esp, edx\r
+\r
+ ;\r
+ ; Push the hob list pointer\r
+ ;\r
+ push eax\r
+\r
+ ;\r
+ ; Save the value\r
+ ; ECX: start of range\r
+ ; EDX: end of range\r
+ ;\r
+ mov ebp, esp\r
+ push ecx\r
+ push edx\r
+\r
+ ;\r
+ ; Push processor count to stack first, then BIST status (AP then BSP)\r
+ ;\r
+ mov eax, 1\r
+ cpuid\r
+ shr ebx, 16\r
+ and ebx, 0000000FFh\r
+ cmp bl, 1\r
+ jae PushProcessorCount\r
+\r
+ ;\r
+ ; Some processors report 0 logical processors. Effectively 0 = 1.\r
+ ; So we fix up the processor count\r
+ ;\r
+ inc ebx\r
+\r
+PushProcessorCount:\r
+ push ebx\r
+\r
+ ;\r
+ ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r
+ ; for all processor threads\r
+ ;\r
+ xor ecx, ecx\r
+ mov cl, bl\r
+PushBist:\r
+ movd eax, mm0\r
+ push eax\r
+ loop PushBist\r
+\r
+ ; Save Time-Stamp Counter\r
+ movd eax, mm5\r
+ push eax\r
+\r
+ movd eax, mm6\r
+ push eax\r
+\r
+ ;\r
+ ; Pass entry point of the PEI core\r
+ ;\r
+ mov edi, 0FFFFFFE0h\r
+ push DWORD PTR ds:[edi]\r
+\r
+ ;\r
+ ; Pass BFV into the PEI Core\r
+ ;\r
+ mov edi, 0FFFFFFFCh\r
+ push DWORD PTR ds:[edi]\r
+\r
+ ;\r
+ ; Pass stack size into the PEI Core\r
+ ;\r
+ mov ecx, [ebp - 4]\r
+ mov edx, [ebp - 8]\r
+ push ecx ; RamBase\r
+\r
+ sub edx, ecx\r
+ push edx ; RamSize\r
+\r
+ ;\r
+ ; Pass Control into the PEI Core\r
+ ;\r
+ call SecStartup\r
+CallPeiCoreEntryPoint ENDP\r
+\r
+END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# SecEntry.S\r
+#\r
+# Abstract:\r
+#\r
+# This is the code that goes from real-mode to protected mode.\r
+# It consumes the reset vector, calls TempRamInit API from FSP binary.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include "Fsp.h"\r
+\r
+ASM_GLOBAL ASM_PFX(_TEXT_REALMODE)\r
+ASM_PFX(_TEXT_REALMODE):\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: _ModuleEntryPoint\r
+#\r
+# Input: None\r
+#\r
+# Output: None\r
+#\r
+# Destroys: Assume all registers\r
+#\r
+# Description:\r
+#\r
+# Transition to non-paged flat-model protected mode from a\r
+# hard-coded GDT that provides exactly two descriptors.\r
+# This is a bare bones transition to protected mode only\r
+# used for a while in PEI and possibly DXE.\r
+#\r
+# After enabling protected mode, a far jump is executed to\r
+# transfer to PEI using the newly loaded GDT.\r
+#\r
+# Return: None\r
+#\r
+# MMX Usage:\r
+# MM0 = BIST State\r
+# MM5 = Save time-stamp counter value high32bit\r
+# MM6 = Save time-stamp counter value low32bit.\r
+#\r
+#----------------------------------------------------------------------------\r
+\r
+.align 4\r
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)\r
+ASM_PFX(_ModuleEntryPoint):\r
+ fninit # clear any pending Floating point exceptions\r
+ #\r
+ # Store the BIST value in mm0\r
+ #\r
+ movd %eax, %mm0\r
+\r
+ #\r
+ # Save time-stamp counter value\r
+ # rdtsc load 64bit time-stamp counter to EDX:EAX\r
+ #\r
+ rdtsc\r
+ movd %edx, %mm5\r
+ movd %ecx, %mm6\r
+\r
+ #\r
+ # Load the GDT table in GdtDesc\r
+ #\r
+ movl $GdtDesc, %esi\r
+ .byte 0x66\r
+ lgdt %cs:(%si)\r
+\r
+ #\r
+ # Transition to 16 bit protected mode\r
+ #\r
+ movl %cr0, %eax # Get control register 0\r
+ orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)\r
+ movl %eax, %cr0 # Activate protected mode\r
+\r
+ movl %cr4, %eax # Get control register 4\r
+ orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
+ movl %eax, %cr4\r
+\r
+ #\r
+ # Now we're in 16 bit protected mode\r
+ # Set up the selectors for 32 bit protected mode entry\r
+ #\r
+ movw SYS_DATA_SEL, %ax\r
+ movw %ax, %ds\r
+ movw %ax, %es\r
+ movw %ax, %fs\r
+ movw %ax, %gs\r
+ movw %ax, %ss\r
+\r
+ #\r
+ # Transition to Flat 32 bit protected mode\r
+ # The jump to a far pointer causes the transition to 32 bit mode\r
+ #\r
+ movl $ProtectedModeEntryLinearAddress, %esi\r
+ jmp *%cs:(%si)\r
+\r
+ASM_GLOBAL ASM_PFX(_TEXT_PROTECTED_MODE)\r
+ASM_PFX(_TEXT_PROTECTED_MODE):\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: ProtectedModeEntryPoint\r
+#\r
+# Input: None\r
+#\r
+# Output: None\r
+#\r
+# Destroys: Assume all registers\r
+#\r
+# Description:\r
+#\r
+# This function handles:\r
+# Call two basic APIs from FSP binary\r
+# Initializes stack with some early data (BIST, PEI entry, etc)\r
+#\r
+# Return: None\r
+#\r
+#----------------------------------------------------------------------------\r
+\r
+.align 4\r
+ASM_GLOBAL ASM_PFX(ProtectedModeEntryPoint)\r
+ASM_PFX(ProtectedModeEntryPoint):\r
+\r
+ # Find the fsp info header\r
+ movl PcdGet32 (PcdFlashFvFspBase), %edi\r
+ movl PcdGet32 (PcdFlashFvFspSize), %ecx\r
+\r
+ movl FVH_SIGINATURE_OFFSET(%edi), %eax\r
+ cmp $FVH_SIGINATURE_VALID_VALUE, %eax\r
+ jnz FspHeaderNotFound\r
+\r
+ xorl %eax, %eax\r
+ movw FVH_EXTHEADER_OFFSET_OFFSET(%edi), %ax\r
+ cmp %ax, 0\r
+ jnz FspFvExtHeaderExist\r
+\r
+ xorl %eax, %eax\r
+ movw FVH_HEADER_LENGTH_OFFSET(%edi), %ax # Bypass Fv Header\r
+ addl %eax, %edi\r
+ jmp FspCheckFfsHeader\r
+\r
+FspFvExtHeaderExist:\r
+ addl %eax, %edi\r
+ movl FVH_EXTHEADER_SIZE_OFFSET(%edi), %eax # Bypass Ext Fv Header\r
+ addl %eax, %edi\r
+\r
+ # Round up to 8 byte alignment\r
+ movl %edi, %eax\r
+ andb $0x07, %al\r
+ jz FspCheckFfsHeader\r
+\r
+ and $0xFFFFFFF8, %edi\r
+ add $0x08, %edi\r
+\r
+FspCheckFfsHeader:\r
+ # Check the ffs guid\r
+ movl (%edi), %eax\r
+ cmp $FSP_HEADER_GUID_DWORD1, %eax\r
+ jnz FspHeaderNotFound\r
+\r
+ movl 0x4(%edi), %eax\r
+ cmp $FSP_HEADER_GUID_DWORD2, %eax\r
+ jnz FspHeaderNotFound\r
+\r
+ movl 0x08(%edi), %eax\r
+ cmp $FSP_HEADER_GUID_DWORD3, %eax\r
+ jnz FspHeaderNotFound\r
+\r
+ movl 0x0c(%edi), %eax\r
+ cmp $FSP_HEADER_GUID_DWORD4, %eax\r
+ jnz FspHeaderNotFound\r
+\r
+ add $FFS_HEADER_SIZE_VALUE, %edi # Bypass the ffs header\r
+\r
+ # Check the section type as raw section\r
+ movb SECTION_HEADER_TYPE_OFFSET(%edi), %al\r
+ cmp $0x19, %al\r
+ jnz FspHeaderNotFound\r
+\r
+ addl $RAW_SECTION_HEADER_SIZE_VALUE, %edi # Bypass the section header\r
+ jmp FspHeaderFound\r
+\r
+FspHeaderNotFound:\r
+ jmp .\r
+\r
+FspHeaderFound:\r
+ # Get the fsp TempRamInit Api address\r
+ movl FSP_HEADER_IMAGEBASE_OFFSET(%edi), %eax\r
+ addl FSP_HEADER_TEMPRAMINIT_OFFSET(%edi), %eax\r
+\r
+ # Setup the hardcode stack\r
+ movl $TempRamInitStack, %esp\r
+\r
+ # Call the fsp TempRamInit Api\r
+ jmp *%eax\r
+\r
+TempRamInitDone:\r
+ cmp $0x0, %eax\r
+ jnz FspApiFailed\r
+\r
+ # ECX: start of range\r
+ # EDX: end of range\r
+ movl %edx, %esp\r
+ pushl %edx\r
+ pushl %ecx\r
+ pushl %eax # zero - no hob list yet\r
+ call ASM_PFX(CallPeiCoreEntryPoint)\r
+\r
+FspApiFailed:\r
+ jmp .\r
+\r
+.align 0x10\r
+TempRamInitStack:\r
+ .long TempRamInitDone\r
+ .long TempRamInitParams\r
+\r
+#\r
+# ROM-based Global-Descriptor Table for the Tiano PEI Phase\r
+#\r
+.align 16\r
+\r
+#\r
+# GDT[0]: 0x00: Null entry, never used.\r
+#\r
+.equ NULL_SEL, . - GDT_BASE # Selector [0]\r
+GDT_BASE:\r
+BootGdtTable: .long 0\r
+ .long 0\r
+#\r
+# Linear data segment descriptor\r
+#\r
+.equ LINEAR_SEL, . - GDT_BASE # Selector [0x8]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x92 # present, ring 0, data, expand-up, writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+#\r
+# Linear code segment descriptor\r
+#\r
+.equ LINEAR_CODE_SEL, . - GDT_BASE # Selector [0x10]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x9B # present, ring 0, data, expand-up, not-writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+#\r
+# System data segment descriptor\r
+#\r
+.equ SYS_DATA_SEL, . - GDT_BASE # Selector [0x18]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x93 # present, ring 0, data, expand-up, not-writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+\r
+#\r
+# System code segment descriptor\r
+#\r
+.equ SYS_CODE_SEL, . - GDT_BASE # Selector [0x20]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x9A # present, ring 0, data, expand-up, writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+#\r
+# Spare segment descriptor\r
+#\r
+.equ SYS16_CODE_SEL, . - GDT_BASE # Selector [0x28]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0x0E # Changed from F000 to E000.\r
+ .byte 0x9B # present, ring 0, code, expand-up, writable\r
+ .byte 0x00 # byte-granular, 16-bit\r
+ .byte 0\r
+#\r
+# Spare segment descriptor\r
+#\r
+.equ SYS16_DATA_SEL, . - GDT_BASE # Selector [0x30]\r
+ .word 0xFFFF # limit 0xFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x93 # present, ring 0, data, expand-up, not-writable\r
+ .byte 0x00 # byte-granular, 16-bit\r
+ .byte 0\r
+\r
+#\r
+# Spare segment descriptor\r
+#\r
+.equ SPARE5_SEL, . - GDT_BASE # Selector [0x38]\r
+ .word 0 # limit 0\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0 # present, ring 0, data, expand-up, writable\r
+ .byte 0 # page-granular, 32-bit\r
+ .byte 0\r
+.equ GDT_SIZE, . - BootGdtTable # Size, in bytes\r
+\r
+#\r
+# GDT Descriptor\r
+#\r
+GdtDesc: # GDT descriptor\r
+ .word GDT_SIZE - 1 # GDT limit\r
+ .long BootGdtTable # GDT base address\r
+\r
+ASM_PFX(ProtectedModeEntryLinearAddress):\r
+ProtectedModeEntryLinearOffset:\r
+ .long ProtectedModeEntryPoint # Offset of our 32 bit code\r
+ .word LINEAR_CODE_SEL\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SecEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+; This is the code that goes from real-mode to protected mode.\r
+; It consumes the reset vector, calls TempRamInit API from FSP binary.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+#include "Fsp.h"\r
+\r
+.686p\r
+.xmm\r
+.model small, c\r
+\r
+EXTRN CallPeiCoreEntryPoint:NEAR\r
+EXTRN TempRamInitParams:FAR\r
+\r
+; Pcds\r
+EXTRN PcdGet32 (PcdFlashFvFspBase):DWORD\r
+EXTRN PcdGet32 (PcdFlashFvFspSize):DWORD\r
+\r
+_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'\r
+ ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: _ModuleEntryPoint\r
+;\r
+; Input: None\r
+;\r
+; Output: None\r
+;\r
+; Destroys: Assume all registers\r
+;\r
+; Description:\r
+;\r
+; Transition to non-paged flat-model protected mode from a\r
+; hard-coded GDT that provides exactly two descriptors.\r
+; This is a bare bones transition to protected mode only\r
+; used for a while in PEI and possibly DXE.\r
+;\r
+; After enabling protected mode, a far jump is executed to\r
+; transfer to PEI using the newly loaded GDT.\r
+;\r
+; Return: None\r
+;\r
+; MMX Usage:\r
+; MM0 = BIST State\r
+; MM5 = Save time-stamp counter value high32bit\r
+; MM6 = Save time-stamp counter value low32bit.\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+align 4\r
+_ModuleEntryPoint PROC NEAR C PUBLIC\r
+ fninit ; clear any pending Floating point exceptions\r
+ ;\r
+ ; Store the BIST value in mm0\r
+ ;\r
+ movd mm0, eax\r
+\r
+ ;\r
+ ; Save time-stamp counter value\r
+ ; rdtsc load 64bit time-stamp counter to EDX:EAX\r
+ ;\r
+ rdtsc\r
+ movd mm5, edx\r
+ movd mm6, eax\r
+\r
+ ;\r
+ ; Load the GDT table in GdtDesc\r
+ ;\r
+ mov esi, OFFSET GdtDesc\r
+ DB 66h\r
+ lgdt fword ptr cs:[si]\r
+\r
+ ;\r
+ ; Transition to 16 bit protected mode\r
+ ;\r
+ mov eax, cr0 ; Get control register 0\r
+ or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)\r
+ mov cr0, eax ; Activate protected mode\r
+\r
+ mov eax, cr4 ; Get control register 4\r
+ or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
+ mov cr4, eax\r
+\r
+ ;\r
+ ; Now we're in 16 bit protected mode\r
+ ; Set up the selectors for 32 bit protected mode entry\r
+ ;\r
+ mov ax, SYS_DATA_SEL\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+ mov ss, ax\r
+\r
+ ;\r
+ ; Transition to Flat 32 bit protected mode\r
+ ; The jump to a far pointer causes the transition to 32 bit mode\r
+ ;\r
+ mov esi, offset ProtectedModeEntryLinearAddress\r
+ jmp fword ptr cs:[si]\r
+\r
+_ModuleEntryPoint ENDP\r
+_TEXT_REALMODE ENDS\r
+\r
+_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'\r
+ ASSUME CS:_TEXT_PROTECTED_MODE, DS:_TEXT_PROTECTED_MODE\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: ProtectedModeEntryPoint\r
+;\r
+; Input: None\r
+;\r
+; Output: None\r
+;\r
+; Destroys: Assume all registers\r
+;\r
+; Description:\r
+;\r
+; This function handles:\r
+; Call two basic APIs from FSP binary\r
+; Initializes stack with some early data (BIST, PEI entry, etc)\r
+;\r
+; Return: None\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+align 4\r
+ProtectedModeEntryPoint PROC NEAR PUBLIC\r
+\r
+ ; Find the fsp info header\r
+ mov edi, PcdGet32 (PcdFlashFvFspBase)\r
+ mov ecx, PcdGet32 (PcdFlashFvFspSize)\r
+\r
+ mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]\r
+ cmp eax, FVH_SIGINATURE_VALID_VALUE\r
+ jnz FspHeaderNotFound\r
+\r
+ xor eax, eax\r
+ mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]\r
+ cmp ax, 0\r
+ jnz FspFvExtHeaderExist\r
+\r
+ xor eax, eax\r
+ mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header\r
+ add edi, eax\r
+ jmp FspCheckFfsHeader\r
+\r
+FspFvExtHeaderExist:\r
+ add edi, eax\r
+ mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header\r
+ add edi, eax\r
+\r
+ ; Round up to 8 byte alignment\r
+ mov eax, edi\r
+ and al, 07h\r
+ jz FspCheckFfsHeader\r
+\r
+ and edi, 0FFFFFFF8h\r
+ add edi, 08h\r
+\r
+FspCheckFfsHeader:\r
+ ; Check the ffs guid\r
+ mov eax, dword ptr [edi]\r
+ cmp eax, FSP_HEADER_GUID_DWORD1\r
+ jnz FspHeaderNotFound\r
+\r
+ mov eax, dword ptr [edi + 4]\r
+ cmp eax, FSP_HEADER_GUID_DWORD2\r
+ jnz FspHeaderNotFound\r
+\r
+ mov eax, dword ptr [edi + 8]\r
+ cmp eax, FSP_HEADER_GUID_DWORD3\r
+ jnz FspHeaderNotFound\r
+\r
+ mov eax, dword ptr [edi + 0Ch]\r
+ cmp eax, FSP_HEADER_GUID_DWORD4\r
+ jnz FspHeaderNotFound\r
+\r
+ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header\r
+\r
+ ; Check the section type as raw section\r
+ mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]\r
+ cmp al, 019h\r
+ jnz FspHeaderNotFound\r
+\r
+ add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header\r
+ jmp FspHeaderFound\r
+\r
+FspHeaderNotFound:\r
+ jmp $\r
+\r
+FspHeaderFound:\r
+ ; Get the fsp TempRamInit Api address\r
+ mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]\r
+ add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]\r
+\r
+ ; Setup the hardcode stack\r
+ mov esp, OFFSET TempRamInitStack\r
+\r
+ ; Call the fsp TempRamInit Api\r
+ jmp eax\r
+\r
+TempRamInitDone:\r
+ cmp eax, 0\r
+ jnz FspApiFailed\r
+\r
+ ; ECX: start of range\r
+ ; EDX: end of range\r
+ mov esp, edx\r
+ push edx\r
+ push ecx\r
+ push eax ; zero - no hob list yet\r
+ call CallPeiCoreEntryPoint\r
+\r
+FspApiFailed:\r
+ jmp $\r
+\r
+align 10h\r
+TempRamInitStack:\r
+ DD OFFSET TempRamInitDone\r
+ DD OFFSET TempRamInitParams\r
+\r
+ProtectedModeEntryPoint ENDP\r
+\r
+;\r
+; ROM-based Global-Descriptor Table for the Tiano PEI Phase\r
+;\r
+align 16\r
+PUBLIC BootGdtTable\r
+\r
+;\r
+; GDT[0]: 0x00: Null entry, never used.\r
+;\r
+NULL_SEL EQU $ - GDT_BASE ; Selector [0]\r
+GDT_BASE:\r
+BootGdtTable DD 0\r
+ DD 0\r
+;\r
+; Linear data segment descriptor\r
+;\r
+LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]\r
+ DW 0FFFFh ; limit 0xFFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 092h ; present, ring 0, data, expand-up, writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; Linear code segment descriptor\r
+;\r
+LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]\r
+ DW 0FFFFh ; limit 0xFFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 09Bh ; present, ring 0, data, expand-up, not-writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; System data segment descriptor\r
+;\r
+SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]\r
+ DW 0FFFFh ; limit 0xFFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 093h ; present, ring 0, data, expand-up, not-writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+\r
+;\r
+; System code segment descriptor\r
+;\r
+SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]\r
+ DW 0FFFFh ; limit 0xFFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 09Ah ; present, ring 0, data, expand-up, writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; Spare segment descriptor\r
+;\r
+SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]\r
+ DW 0FFFFh ; limit 0xFFFFF\r
+ DW 0 ; base 0\r
+ DB 0Eh ; Changed from F000 to E000.\r
+ DB 09Bh ; present, ring 0, code, expand-up, writable\r
+ DB 00h ; byte-granular, 16-bit\r
+ DB 0\r
+;\r
+; Spare segment descriptor\r
+;\r
+SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 093h ; present, ring 0, data, expand-up, not-writable\r
+ DB 00h ; byte-granular, 16-bit\r
+ DB 0\r
+\r
+;\r
+; Spare segment descriptor\r
+;\r
+SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]\r
+ DW 0 ; limit 0\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 0 ; present, ring 0, data, expand-up, writable\r
+ DB 0 ; page-granular, 32-bit\r
+ DB 0\r
+GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes\r
+\r
+;\r
+; GDT Descriptor\r
+;\r
+GdtDesc: ; GDT descriptor\r
+ DW GDT_SIZE - 1 ; GDT limit\r
+ DD OFFSET BootGdtTable ; GDT base address\r
+\r
+\r
+ProtectedModeEntryLinearAddress LABEL FWORD\r
+ProtectedModeEntryLinearOffset LABEL DWORD\r
+ DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code\r
+ DW LINEAR_CODE_SEL\r
+\r
+_TEXT_PROTECTED_MODE ENDS\r
+END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Abstract:\r
+#\r
+# Switch the stack from temporary memory to permenent memory.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# SecSwitchStack (\r
+# UINT32 TemporaryMemoryBase,\r
+# UINT32 PermenentMemoryBase\r
+# )#\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX (SecSwitchStack)\r
+ASM_PFX(SecSwitchStack):\r
+ #\r
+ # Save standard registers so they can be used to change stack\r
+ #\r
+ pushl %eax\r
+ pushl %ebx\r
+ pushl %ecx\r
+ pushl %edx\r
+\r
+ #\r
+ # !!CAUTION!! this function address's is pushed into stack after\r
+ # migration of whole temporary memory, so need save it to permenent\r
+ # memory at first!\r
+ #\r
+ movl 20(%esp), %ebx # Save the first parameter\r
+ movl 24(%esp), %ecx # Save the second parameter\r
+\r
+ #\r
+ # Save this function's return address into permenent memory at first.\r
+ # Then, Fixup the esp point to permenent memory\r
+ #\r
+ movl %esp, %eax\r
+ subl %ebx, %eax\r
+ addl %ecx, %eax\r
+ movl 0(%esp), %edx # copy pushed register's value to permenent memory\r
+ movl %edx, 0(%eax)\r
+ movl 4(%esp), %edx\r
+ movl %edx, 4(%eax)\r
+ movl 8(%esp), %edx\r
+ movl %edx, 8(%eax)\r
+ movl 12(%esp), %edx\r
+ movl %edx, 12(%eax)\r
+ movl 16(%esp), %edx # Update this function's return address into permenent memory\r
+ movl %edx, 16(%eax)\r
+ movl %eax, %esp # From now, esp is pointed to permenent memory\r
+\r
+ #\r
+ # Fixup the ebp point to permenent memory\r
+ #\r
+ movl %ebp, %eax\r
+ subl %ebx, %eax\r
+ addl %ecx, %eax\r
+ movl %eax, %ebp # From now, ebp is pointed to permenent memory\r
+\r
+ popl %edx\r
+ popl %ecx\r
+ popl %ebx\r
+ popl %eax\r
+ ret\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Abstract:\r
+;\r
+; Switch the stack from temporary memory to permenent memory.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .586p\r
+ .model flat,C\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; SecSwitchStack (\r
+; UINT32 TemporaryMemoryBase,\r
+; UINT32 PermenentMemoryBase\r
+; );\r
+;------------------------------------------------------------------------------\r
+SecSwitchStack PROC\r
+ ;\r
+ ; Save three register: eax, ebx, ecx\r
+ ;\r
+ push eax\r
+ push ebx\r
+ push ecx\r
+ push edx\r
+\r
+ ;\r
+ ; !!CAUTION!! this function address's is pushed into stack after\r
+ ; migration of whole temporary memory, so need save it to permenent\r
+ ; memory at first!\r
+ ;\r
+\r
+ mov ebx, [esp + 20] ; Save the first parameter\r
+ mov ecx, [esp + 24] ; Save the second parameter\r
+\r
+ ;\r
+ ; Save this function's return address into permenent memory at first.\r
+ ; Then, Fixup the esp point to permenent memory\r
+ ;\r
+ mov eax, esp\r
+ sub eax, ebx\r
+ add eax, ecx\r
+ mov edx, dword ptr [esp] ; copy pushed register's value to permenent memory\r
+ mov dword ptr [eax], edx\r
+ mov edx, dword ptr [esp + 4]\r
+ mov dword ptr [eax + 4], edx\r
+ mov edx, dword ptr [esp + 8]\r
+ mov dword ptr [eax + 8], edx\r
+ mov edx, dword ptr [esp + 12]\r
+ mov dword ptr [eax + 12], edx\r
+ mov edx, dword ptr [esp + 16] ; Update this function's return address into permenent memory\r
+ mov dword ptr [eax + 16], edx\r
+ mov esp, eax ; From now, esp is pointed to permenent memory\r
+\r
+ ;\r
+ ; Fixup the ebp point to permenent memory\r
+ ;\r
+ mov eax, ebp\r
+ sub eax, ebx\r
+ add eax, ecx\r
+ mov ebp, eax ; From now, ebp is pointed to permenent memory\r
+\r
+ pop edx\r
+ pop ecx\r
+ pop ebx\r
+ pop eax\r
+ ret\r
+SecSwitchStack ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ Sample to provide platform init function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiPei.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+ Platform initialization.\r
+\r
+ @param[in] FspHobList HobList produced by FSP.\r
+ @param[in] StartOfRange Start of temporary RAM.\r
+ @param[in] EndOfRange End of temporary RAM.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformInit (\r
+ IN VOID *FspHobList,\r
+ IN VOID *StartOfRange,\r
+ IN VOID *EndOfRange\r
+ )\r
+{\r
+ //\r
+ // Platform initialization\r
+ // Enable Serial port here\r
+ //\r
+\r
+ DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam\n"));\r
+ DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));\r
+ DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));\r
+ DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));\r
+}\r
--- /dev/null
+/** @file\r
+ Sample to provide SaveSecContext function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiPei.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+#include <Ppi/SecPlatformInformation.h>\r
+\r
+/**\r
+ Save BIST value before call FspInit.\r
+\r
+ @param[in] Bist BIST value.\r
+**/\r
+VOID\r
+AsmSaveBistValue (\r
+ IN UINT32 Bist\r
+ );\r
+\r
+/**\r
+ Save Ticker value before call FspInit.\r
+\r
+ @param[in] Ticker Ticker value.\r
+**/\r
+VOID\r
+AsmSaveTickerValue (\r
+ IN UINT64 Ticker\r
+ );\r
+\r
+/**\r
+ Save SEC context before call FspInit.\r
+\r
+ @param[in] PeiServices Pointer to PEI Services Table.\r
+**/\r
+VOID\r
+EFIAPI\r
+SaveSecContext (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ UINT32 *Bist;\r
+ UINT64 *Ticker;\r
+ UINT32 Size;\r
+ UINT32 Count;\r
+ UINT32 TopOfTemporaryRam;\r
+ VOID *TopOfTemporaryRamPpi;\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((DEBUG_INFO, "SaveSecContext - 0x%x\n", PeiServices));\r
+\r
+ Status = (*PeiServices)->LocatePpi (\r
+ PeiServices,\r
+ &gTopOfTemporaryRamPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &TopOfTemporaryRamPpi\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return ;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO, "TopOfTemporaryRamPpi - 0x%x\n", TopOfTemporaryRamPpi));\r
+\r
+ //\r
+ // The entries of BIST information, together with the number of them,\r
+ // reside in the bottom of stack, left untouched by normal stack operation.\r
+ // This routine copies the BIST information to the buffer pointed by\r
+ // PlatformInformationRecord for output.\r
+ //\r
+ // |--------------| <- TopOfTemporaryRam\r
+ // |Number of BSPs|\r
+ // |--------------|\r
+ // | BIST |\r
+ // |--------------|\r
+ // | .... |\r
+ // |--------------|\r
+ // | TSC[63:32] |\r
+ // |--------------|\r
+ // | TSC[31:00] |\r
+ // |--------------|\r
+ //\r
+\r
+ TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);\r
+ TopOfTemporaryRam -= sizeof(UINT32) * 2;\r
+ DEBUG ((DEBUG_INFO, "TopOfTemporaryRam - 0x%x\n", TopOfTemporaryRam));\r
+ Count = *(UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32));\r
+ DEBUG ((DEBUG_INFO, "Count - 0x%x\n", Count));\r
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);\r
+ DEBUG ((DEBUG_INFO, "Size - 0x%x\n", Size));\r
+\r
+ Bist = (UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size);\r
+ DEBUG ((DEBUG_INFO, "Bist - 0x%x\n", *Bist));\r
+ Ticker = (UINT64 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size - sizeof(UINT64));\r
+ DEBUG ((DEBUG_INFO, "Ticker - 0x%lx\n", *Ticker));\r
+\r
+ // Just need record BSP\r
+ AsmSaveBistValue (*Bist);\r
+ AsmSaveTickerValue (*Ticker);\r
+}\r
--- /dev/null
+/** @file\r
+ Sample to provide SecGetPerformance function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPerformance.h>\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+ This interface conveys performance information out of the Security (SEC) phase into PEI.\r
+\r
+ This service is published by the SEC phase. The SEC phase handoff has an optional\r
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the\r
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,\r
+ this information is encapsulated into the data structure abstracted by this service.\r
+ This information is collected for the boot-strap processor (BSP) on IA-32.\r
+\r
+ @param[in] PeiServices The pointer to the PEI Services Table.\r
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.\r
+ @param[out] Performance The pointer to performance data collected in SEC phase.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecGetPerformance (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_SEC_PERFORMANCE_PPI *This,\r
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance\r
+ )\r
+{\r
+ UINT32 Size;\r
+ UINT32 Count;\r
+ UINT32 TopOfTemporaryRam;\r
+ UINT64 Ticker;\r
+ VOID *TopOfTemporaryRamPpi;\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));\r
+\r
+ Status = (*PeiServices)->LocatePpi (\r
+ PeiServices,\r
+ &gTopOfTemporaryRamPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &TopOfTemporaryRamPpi\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // |--------------| <- TopOfTemporaryRam\r
+ // |Number of BSPs|\r
+ // |--------------|\r
+ // | BIST |\r
+ // |--------------|\r
+ // | .... |\r
+ // |--------------|\r
+ // | TSC[63:32] |\r
+ // |--------------|\r
+ // | TSC[31:00] |\r
+ // |--------------|\r
+ //\r
+ TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);\r
+ TopOfTemporaryRam -= sizeof(UINT32) * 2;\r
+ Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));\r
+ Size = Count * sizeof (UINT64);\r
+\r
+ Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);\r
+ Performance->ResetEnd = GetTimeInNanoSecond (Ticker);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Sample to provide FSP wrapper platform sec related function.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SecPeiFspPlatformSecLibSample\r
+ FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = FspPlatformSecLib\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+ FspPlatformSecLibSample.c\r
+ SecRamInitData.c\r
+ SaveSecContext.c\r
+ SecPlatformInformation.c\r
+ SecGetPerformance.c\r
+ SecTempRamSupport.c\r
+ PlatformInit.c\r
+\r
+[Sources.IA32]\r
+ Ia32/SecEntry.asm\r
+ Ia32/PeiCoreEntry.asm\r
+ Ia32/AsmSaveSecContext.asm\r
+ Ia32/Stack.asm\r
+\r
+ Ia32/SecEntry.S\r
+ Ia32/PeiCoreEntry.S\r
+ Ia32/AsmSaveSecContext.S\r
+ Ia32/Stack.S\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ IntelFspPkg/IntelFspPkg.dec\r
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+ LocalApicLib\r
+\r
+[Ppis]\r
+ gEfiSecPlatformInformationPpiGuid\r
+ gPeiSecPerformancePpiGuid\r
+ gEfiTemporaryRamSupportPpiGuid\r
+\r
+[Pcd]\r
+ gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase\r
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize\r
+\r
+[FixedPcd]\r
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress\r
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize\r
+ gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset\r
+ gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress\r
+ gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize\r
--- /dev/null
+/** @file\r
+ Sample to provide SecPlatformInformation function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+ This interface conveys state information out of the Security (SEC) phase into PEI.\r
+\r
+ @param[in] PeiServices Pointer to the PEI Services Table.\r
+ @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.\r
+ @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPlatformInformation (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN OUT UINT64 *StructureSize,\r
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
+ )\r
+{\r
+ UINT32 *Bist;\r
+ UINT32 Size;\r
+ UINT32 Count;\r
+ UINT32 TopOfTemporaryRam;\r
+ VOID *TopOfTemporaryRamPpi;\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));\r
+\r
+ Status = (*PeiServices)->LocatePpi (\r
+ PeiServices,\r
+ &gTopOfTemporaryRamPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &TopOfTemporaryRamPpi\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // The entries of BIST information, together with the number of them,\r
+ // reside in the bottom of stack, left untouched by normal stack operation.\r
+ // This routine copies the BIST information to the buffer pointed by\r
+ // PlatformInformationRecord for output.\r
+ //\r
+ TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);\r
+ TopOfTemporaryRam -= sizeof(UINT32) * 2;\r
+ Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));\r
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);\r
+\r
+ if ((*StructureSize) < (UINT64) Size) {\r
+ *StructureSize = Size;\r
+ return EFI_BUFFER_TOO_SMALL;\r
+ }\r
+\r
+ *StructureSize = Size;\r
+ Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);\r
+\r
+ CopyMem (PlatformInformationRecord, Bist, Size);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ Sample to provide TempRamInitParams data.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/PcdLib.h>\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 TempRamInitParams[4] = {\r
+ ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicroCodeOffset)),\r
+ ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicroCodeOffset)),\r
+ FixedPcdGet32 (PcdFlashCodeCacheAddress),\r
+ FixedPcdGet32 (PcdFlashCodeCacheSize)\r
+};\r
--- /dev/null
+/** @file\r
+ Sample to provide SecTemporaryRamSupport function.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/TemporaryRamSupport.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+/**\r
+ Switch the stack in the temporary memory to the one in the permanent memory.\r
+\r
+ This function must be invoked after the memory migration immediately. The relative\r
+ position of the stack in the temporary and permanent memory is same.\r
+\r
+ @param[in] TemporaryMemoryBase Base address of the temporary memory.\r
+ @param[in] PermenentMemoryBase Base address of the permanent memory.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecSwitchStack (\r
+ IN UINT32 TemporaryMemoryBase,\r
+ IN UINT32 PermenentMemoryBase\r
+ );\r
+\r
+/**\r
+ This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+ permanent memory.\r
+\r
+ @param[in] PeiServices Pointer to the PEI Services Table.\r
+ @param[in] TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param[in] PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param[in] CopySize Amount of memory to migrate from temporary to permanent memory.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+ TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ )\r
+{\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ VOID* OldHeap;\r
+ VOID* NewHeap;\r
+ VOID* OldStack;\r
+ VOID* NewStack;\r
+ DEBUG_AGENT_CONTEXT_POSTMEM_SEC DebugAgentContext;\r
+ BOOLEAN OldStatus;\r
+ UINTN PeiStackSize;\r
+\r
+ PeiStackSize = (UINTN)PcdGet32 (PcdPeiTemporaryRamStackSize);\r
+ if (PeiStackSize == 0) {\r
+ PeiStackSize = (CopySize >> 1);\r
+ }\r
+\r
+ ASSERT (PeiStackSize < CopySize);\r
+\r
+ //\r
+ // |-------------------|---->\r
+ // | Stack | PeiStackSize\r
+ // |-------------------|---->\r
+ // | Heap | PeiTemporayRamSize\r
+ // |-------------------|----> TempRamBase\r
+ //\r
+ // |-------------------|---->\r
+ // | Heap | PeiTemporayRamSize\r
+ // |-------------------|---->\r
+ // | Stack | PeiStackSize\r
+ // |-------------------|----> PermanentMemoryBase\r
+ //\r
+\r
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + PeiStackSize);\r
+\r
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize - PeiStackSize);\r
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+\r
+ DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap - (UINTN)OldHeap;\r
+ DebugAgentContext.StackMigrateOffset = (UINTN)NewStack - (UINTN)OldStack;\r
+\r
+ OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);\r
+ //\r
+ // Initialize Debug Agent to support source level debug in PEI phase after memory ready.\r
+ // It will build HOB and fix up the pointer in IDT table.\r
+ //\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *) &DebugAgentContext, NULL);\r
+\r
+ //\r
+ // Migrate Heap\r
+ //\r
+ CopyMem (NewHeap, OldHeap, CopySize - PeiStackSize);\r
+\r
+ //\r
+ // Migrate Stack\r
+ //\r
+ CopyMem (NewStack, OldStack, PeiStackSize);\r
+\r
+\r
+ //\r
+ // We need *not* fix the return address because currently,\r
+ // The PeiCore is executed in flash.\r
+ //\r
+\r
+ //\r
+ // Rebase IDT table in permanent memory\r
+ //\r
+ AsmReadIdtr (&IdtDescriptor);\r
+ IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;\r
+\r
+ AsmWriteIdtr (&IdtDescriptor);\r
+\r
+\r
+ //\r
+ // Program MTRR\r
+ //\r
+\r
+ //\r
+ // SecSwitchStack function must be invoked after the memory migration\r
+ // immediatly, also we need fixup the stack change caused by new call into\r
+ // permenent memory.\r
+ //\r
+ SecSwitchStack (\r
+ (UINT32) (UINTN) OldStack,\r
+ (UINT32) (UINTN) NewStack\r
+ );\r
+\r
+ SaveAndSetDebugTimerInterrupt (OldStatus);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
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