While the alternative PEI-less SEC implementation in PrePi already
takes the EnableVFP PCD into account, the PrePeiCore code does not,
and so we may end up triggering synchronous exception when code
attempts to use FP or SIMD registers, which is permitted on AARCH64
by the spec.
So enable the VFP as early as feasible if the associated PCD is set.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
+ // Enable Floating Point\r
+ if (FixedPcdGet32 (PcdVFPEnabled)) {\r
+ ArmEnableVFP ();\r
+ }\r
+\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
// If not primary Jump to Secondary Main\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
gArmTokenSpaceGuid.PcdFvSize\r
+ gArmTokenSpaceGuid.PcdVFPEnabled\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
gArmTokenSpaceGuid.PcdFvSize\r
+ gArmTokenSpaceGuid.PcdVFPEnabled\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\r