+/** @file\r
+ Flush the cache is required for most architectures while do capsule\r
+ update. It is not support at Runtime.\r
+\r
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CapsuleService.h"\r
+\r
+#include <Library/CacheMaintenanceLib.h>\r
+\r
+/**\r
+ Writes Back a range of data cache lines covering a set of capsules in memory.\r
+\r
+ Writes Back the data cache lines specified by ScatterGatherList.\r
+\r
+ @param ScatterGatherList Physical address of the data structure that\r
+ describes a set of capsules in memory\r
+\r
+**/\r
+VOID\r
+CapsuleCacheWriteBack (\r
+ IN EFI_PHYSICAL_ADDRESS ScatterGatherList\r
+ )\r
+{\r
+ EFI_CAPSULE_BLOCK_DESCRIPTOR *Desc;\r
+\r
+ if (!EfiAtRuntime ()) {\r
+ Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)ScatterGatherList;\r
+ do {\r
+ WriteBackDataCacheRange (\r
+ (VOID *)(UINTN)Desc,\r
+ (UINTN)sizeof (*Desc)\r
+ );\r
+\r
+ if (Desc->Length > 0) {\r
+ WriteBackDataCacheRange (\r
+ (VOID *)(UINTN)Desc->Union.DataBlock,\r
+ (UINTN)Desc->Length\r
+ );\r
+ Desc++;\r
+ } else if (Desc->Union.ContinuationPointer > 0) {\r
+ Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)Desc->Union.ContinuationPointer;\r
+ }\r
+ } while (Desc->Length > 0 || Desc->Union.ContinuationPointer > 0);\r
+\r
+ WriteBackDataCacheRange (\r
+ (VOID *)(UINTN)Desc,\r
+ (UINTN)sizeof (*Desc)\r
+ );\r
+ }\r
+}\r
+\r