OvmfPkg/XenResetVector: Add new entry point for Xen PVH

Add a new entry point for Xen PVH that enter directly in 32bits.

Information on the expected state of the machine when this entry point
is used can be found at:
https://xenbits.xenproject.org/docs/unstable/misc/pvh.html

Also, compare to the original file [1], the two `nop' of the "resetVector"
entry point are removed. There were introduced by 8332983e2e33
("UefiCpuPkg: Replace the un-necessary WBINVD instruction at the reset
vector with two NOPs in VTF0.", 2011-08-04), but don't seems to be
useful. This is the entry point used by HVM guest (hvmloader).

[1] UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20190813113119.14804-7-anthony.perard@citrix.com>

diff --git a/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm
new file mode 100644 (file)
index 0000000..56749bd
--- /dev/null
+++ b/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm
@@ -0,0 +1,79 @@
+;------------------------------------------------------------------------------\r
+; @file\r
+; First code executed by processor after resetting.\r
+;\r
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2019, Citrix Systems, Inc.\r
+;\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS    16\r
+\r
+ALIGN   16\r
+\r
+;\r
+; Pad the image size to 4k when page tables are in VTF0\r
+;\r
+; If the VTF0 image has page tables built in, then we need to make\r
+; sure the end of VTF0 is 4k above where the page tables end.\r
+;\r
+; This is required so the page tables will be 4k aligned when VTF0 is\r
+; located just below 0x100000000 (4GB) in the firmware device.\r
+;\r
+%ifdef ALIGN_TOP_TO_4K_FOR_PAGING\r
+    TIMES (0x1000 - ($ - EndOfPageTables) - (fourGigabytes - xenPVHEntryPoint)) DB 0\r
+%endif\r
+\r
+BITS    32\r
+xenPVHEntryPoint:\r
+;\r
+; Entry point to use when running as a Xen PVH guest. (0xffffffd0)\r
+;\r
+; Description of the expected state of the machine when this entry point is\r
+; used can be found at:\r
+; https://xenbits.xenproject.org/docs/unstable/misc/pvh.html\r
+;\r
+    jmp     xenPVHMain\r
+\r
+BITS    16\r
+ALIGN   16\r
+\r
+applicationProcessorEntryPoint:\r
+;\r
+; Application Processors entry point\r
+;\r
+; GenFv generates code aligned on a 4k boundary which will jump to this\r
+; location.  (0xffffffe0)  This allows the Local APIC Startup IPI to be\r
+; used to wake up the application processors.\r
+;\r
+    jmp     EarlyApInitReal16\r
+\r
+ALIGN   8\r
+\r
+    DD      0\r
+\r
+;\r
+; The VTF signature\r
+;\r
+; VTF-0 means that the VTF (Volume Top File) code does not require\r
+; any fixups.\r
+;\r
+vtfSignature:\r
+    DB      'V', 'T', 'F', 0\r
+\r
+ALIGN   16\r
+\r
+resetVector:\r
+;\r
+; Reset Vector\r
+;\r
+; This is where the processor will begin execution\r
+;\r
+    jmp     EarlyBspInitReal16\r
+\r
+ALIGN   16\r
+\r
+fourGigabytes:\r
+\r

diff --git a/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm
new file mode 100644 (file)
index 0000000..2a17fed
--- /dev/null
+++ b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm
@@ -0,0 +1,49 @@
+;------------------------------------------------------------------------------\r
+; @file\r
+; An entry point use by Xen when a guest is started in PVH mode.\r
+;\r
+; Copyright (c) 2019, Citrix Systems, Inc.\r
+;\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS    32\r
+\r
+xenPVHMain:\r
+    ;\r
+    ; 'BP' to indicate boot-strap processor\r
+    ;\r
+    mov     di, 'BP'\r
+\r
+    ;\r
+    ; ESP will be used as initial value of the EAX register\r
+    ; in Main.asm\r
+    ;\r
+    xor     esp, esp\r
+\r
+    mov     ebx, ADDR_OF(gdtr)\r
+    lgdt    [ebx]\r
+\r
+    mov     eax, SEC_DEFAULT_CR0\r
+    mov     cr0, eax\r
+\r
+    jmp     LINEAR_CODE_SEL:ADDR_OF(.jmpToNewCodeSeg)\r
+.jmpToNewCodeSeg:\r
+\r
+    mov     eax, SEC_DEFAULT_CR4\r
+    mov     cr4, eax\r
+\r
+    mov     ax, LINEAR_SEL\r
+    mov     ds, ax\r
+    mov     es, ax\r
+    mov     fs, ax\r
+    mov     gs, ax\r
+    mov     ss, ax\r
+\r
+    ;\r
+    ; Jump to the main routine of the pre-SEC code\r
+    ; skiping the 16-bit part of the routine and\r
+    ; into the 32-bit flat mode part\r
+    ;\r
+    OneTimeCallRet TransitionFromReal16To32BitFlat\r

diff --git a/OvmfPkg/XenResetVector/XenResetVector.nasmb b/OvmfPkg/XenResetVector/XenResetVector.nasmb
index 89a4b08bc3b0add59a30d4f706969c1d3d06bbff..0dbc4f2c1dea3bb4869e61dea8778eac9b5b1b43 100644 (file)
--- a/OvmfPkg/XenResetVector/XenResetVector.nasmb
+++ b/OvmfPkg/XenResetVector/XenResetVector.nasmb
@@ -63,6 +63,7 @@
 %include "Ia16/Init16.asm"\r
 \r
 %include "Main.asm"\r
+%include "Ia32/XenPVHMain.asm"\r
 \r
 %include "Ia16/ResetVectorVtf0.asm"\r
 \r