+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Library/ArmShellCmdLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/VirtioMmioDeviceLib.h>\r
-\r
-#include <VExpressMotherBoard.h>\r
-\r
-#define ARM_FVP_BASE_VIRTIO_BLOCK_BASE 0x1c130000\r
-\r
-#pragma pack(1)\r
-typedef struct {\r
- VENDOR_DEVICE_PATH Vendor;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} VIRTIO_BLK_DEVICE_PATH;\r
-#pragma pack()\r
-\r
-VIRTIO_BLK_DEVICE_PATH mVirtioBlockDevicePath =\r
-{\r
- {\r
- {\r
- HARDWARE_DEVICE_PATH,\r
- HW_VENDOR_DP,\r
- {\r
- (UINT8)( sizeof(VENDOR_DEVICE_PATH) ),\r
- (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)\r
- }\r
- },\r
- EFI_CALLER_ID_GUID,\r
- },\r
- {\r
- END_DEVICE_PATH_TYPE,\r
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
- {\r
- sizeof (EFI_DEVICE_PATH_PROTOCOL),\r
- 0\r
- }\r
- }\r
-};\r
-\r
-/**\r
- * Generic UEFI Entrypoint for 'ArmFvpDxe' driver\r
- * See UEFI specification for the details of the parameters\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-ArmFvpInitialise (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- Status = gBS->InstallProtocolInterface (&ImageHandle,\r
- &gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE,\r
- &mVirtioBlockDevicePath);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- // Declare the Virtio BlockIo device\r
- Status = VirtioMmioInstallDevice (ARM_FVP_BASE_VIRTIO_BLOCK_BASE, ImageHandle);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install Virtio block device\n"));\r
- }\r
-\r
- // Install dynamic Shell command to run baremetal binaries.\r
- Status = ShellDynCmdRunAxfInstall (ImageHandle);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install ShellDynCmdRunAxf\n"));\r
- }\r
-\r
- return Status;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010006\r
- BASE_NAME = ArmFvpDxe\r
- FILE_GUID = 405b2307-6839-4d52-aeb9-bece64252800\r
- MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.0\r
- ENTRY_POINT = ArmFvpInitialise\r
-\r
-[Sources.common]\r
- ArmFvpDxe.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- OvmfPkg/OvmfPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmShellCmdRunAxfLib\r
- BaseMemoryLib\r
- UefiDriverEntryPoint\r
- UefiBootServicesTableLib\r
- VirtioMmioDeviceLib\r
-\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Library/ArmShellCmdLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- * Generic UEFI Entrypoint for 'ArmHwDxe' driver\r
- * See UEFI specification for the details of the parameters\r
- */\r
-EFI_STATUS\r
-EFIAPI\r
-ArmHwInitialise (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- // Install dynamic Shell command to run baremetal binaries.\r
- Status = ShellDynCmdRunAxfInstall (ImageHandle);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "ArmHwDxe: Failed to install ShellDynCmdRunAxf\n"));\r
- }\r
-\r
- return Status;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010006\r
- BASE_NAME = ArmHwDxe\r
- FILE_GUID = fe61bb5f-1b67-4c24-b346-73db42e873e5\r
- MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.0\r
- ENTRY_POINT = ArmHwInitialise\r
-\r
-[Sources.common]\r
- ArmHwDxe.c\r
-\r
-[Packages]\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- ArmShellCmdRunAxfLib\r
- DxeServicesTableLib\r
- MemoryAllocationLib\r
- UefiDriverEntryPoint\r
-\r
-[Protocols]\r
- gEfiDevicePathProtocolGuid\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-/*\r
- Implementation of the Android Fastboot Platform protocol, to be used by the\r
- Fastboot UEFI application, for ARM Versatile Express platforms.\r
-*/\r
-\r
-#include <Protocol/AndroidFastbootPlatform.h>\r
-#include <Protocol/BlockIo.h>\r
-#include <Protocol/DiskIo.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DevicePathLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-\r
-#define FLASH_DEVICE_PATH_SIZE(DevPath) ( GetDevicePathSize (DevPath) - \\r
- sizeof (EFI_DEVICE_PATH_PROTOCOL))\r
-\r
-#define PARTITION_NAME_MAX_LENGTH 72/2\r
-\r
-#define IS_ALPHA(Char) (((Char) <= L'z' && (Char) >= L'a') || \\r
- ((Char) <= L'Z' && (Char) >= L'Z'))\r
-\r
-typedef struct _FASTBOOT_PARTITION_LIST {\r
- LIST_ENTRY Link;\r
- CHAR16 PartitionName[PARTITION_NAME_MAX_LENGTH];\r
- EFI_HANDLE PartitionHandle;\r
-} FASTBOOT_PARTITION_LIST;\r
-\r
-STATIC LIST_ENTRY mPartitionListHead;\r
-\r
-/*\r
- Helper to free the partition list\r
-*/\r
-STATIC\r
-VOID\r
-FreePartitionList (\r
- VOID\r
- )\r
-{\r
- FASTBOOT_PARTITION_LIST *Entry;\r
- FASTBOOT_PARTITION_LIST *NextEntry;\r
-\r
- Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);\r
- while (!IsNull (&mPartitionListHead, &Entry->Link)) {\r
- NextEntry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);\r
-\r
- RemoveEntryList (&Entry->Link);\r
- FreePool (Entry);\r
-\r
- Entry = NextEntry;\r
- }\r
-}\r
-/*\r
- Read the PartitionName fields from the GPT partition entries, putting them\r
- into an allocated array that should later be freed.\r
-*/\r
-STATIC\r
-EFI_STATUS\r
-ReadPartitionEntries (\r
- IN EFI_BLOCK_IO_PROTOCOL *BlockIo,\r
- OUT EFI_PARTITION_ENTRY **PartitionEntries\r
- )\r
-{\r
- UINTN EntrySize;\r
- UINTN NumEntries;\r
- UINTN BufferSize;\r
- UINT32 MediaId;\r
- EFI_PARTITION_TABLE_HEADER *GptHeader;\r
- EFI_STATUS Status;\r
-\r
- MediaId = BlockIo->Media->MediaId;\r
-\r
- //\r
- // Read size of Partition entry and number of entries from GPT header\r
- //\r
-\r
- GptHeader = AllocatePool (BlockIo->Media->BlockSize);\r
- if (GptHeader == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- Status = BlockIo->ReadBlocks (BlockIo, MediaId, 1, BlockIo->Media->BlockSize, (VOID *) GptHeader);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- // Check there is a GPT on the media\r
- if (GptHeader->Header.Signature != EFI_PTAB_HEADER_ID ||\r
- GptHeader->MyLBA != 1) {\r
- DEBUG ((EFI_D_ERROR,\r
- "Fastboot platform: No GPT on flash. "\r
- "Fastboot on Versatile Express does not support MBR.\n"\r
- ));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- EntrySize = GptHeader->SizeOfPartitionEntry;\r
- NumEntries = GptHeader->NumberOfPartitionEntries;\r
-\r
- FreePool (GptHeader);\r
-\r
- ASSERT (EntrySize != 0);\r
- ASSERT (NumEntries != 0);\r
-\r
- BufferSize = ALIGN_VALUE (EntrySize * NumEntries, BlockIo->Media->BlockSize);\r
- *PartitionEntries = AllocatePool (BufferSize);\r
- if (PartitionEntries == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- Status = BlockIo->ReadBlocks (BlockIo, MediaId, 2, BufferSize, (VOID *) *PartitionEntries);\r
- if (EFI_ERROR (Status)) {\r
- FreePool (PartitionEntries);\r
- return Status;\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-\r
-/*\r
- Do any initialisation that needs to be done in order to be able to respond to\r
- commands.\r
-\r
- @retval EFI_SUCCESS Initialised successfully.\r
- @retval !EFI_SUCCESS Error in initialisation.\r
-*/\r
-STATIC\r
-EFI_STATUS\r
-ArmFastbootPlatformInit (\r
- VOID\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_DEVICE_PATH_PROTOCOL *FlashDevicePath;\r
- EFI_DEVICE_PATH_PROTOCOL *FlashDevicePathDup;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
- EFI_DEVICE_PATH_PROTOCOL *NextNode;\r
- HARDDRIVE_DEVICE_PATH *PartitionNode;\r
- UINTN NumHandles;\r
- EFI_HANDLE *AllHandles;\r
- UINTN LoopIndex;\r
- EFI_HANDLE FlashHandle;\r
- EFI_BLOCK_IO_PROTOCOL *FlashBlockIo;\r
- EFI_PARTITION_ENTRY *PartitionEntries;\r
- FASTBOOT_PARTITION_LIST *Entry;\r
-\r
- InitializeListHead (&mPartitionListHead);\r
-\r
- //\r
- // Get EFI_HANDLES for all the partitions on the block devices pointed to by\r
- // PcdFastbootFlashDevicePath, also saving their GPT partition labels.\r
- // We will use these labels as the key in ArmFastbootPlatformFlashPartition.\r
- // There's no way to find all of a device's children, so we get every handle\r
- // in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out ones\r
- // that don't represent partitions on the flash device.\r
- //\r
-\r
- FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));\r
-\r
- //\r
- // Open the Disk IO protocol on the flash device - this will be used to read\r
- // partition names out of the GPT entries\r
- //\r
- // Create another device path pointer because LocateDevicePath will modify it.\r
- FlashDevicePathDup = FlashDevicePath;\r
- Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePathDup, &FlashHandle);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));\r
- // Failing to locate partitions should not prevent to do other Android FastBoot actions\r
- return EFI_SUCCESS;\r
- }\r
-\r
- Status = gBS->OpenProtocol (\r
- FlashHandle,\r
- &gEfiBlockIoProtocolGuid,\r
- (VOID **) &FlashBlockIo,\r
- gImageHandle,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "Fastboot platform: Couldn't open Android NVM device (status: %r)\n", Status));\r
- return EFI_DEVICE_ERROR;\r
- }\r
-\r
- // Read the GPT partition entry array into memory so we can get the partition names\r
- Status = ReadPartitionEntries (FlashBlockIo, &PartitionEntries);\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "Warning: Failed to read partitions from Android NVM device (status: %r)\n", Status));\r
- // Failing to locate partitions should not prevent to do other Android FastBoot actions\r
- return EFI_SUCCESS;\r
- }\r
-\r
- // Get every Block IO protocol instance installed in the system\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiBlockIoProtocolGuid,\r
- NULL,\r
- &NumHandles,\r
- &AllHandles\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- // Filter out handles that aren't children of the flash device\r
- for (LoopIndex = 0; LoopIndex < NumHandles; LoopIndex++) {\r
- // Get the device path for the handle\r
- Status = gBS->OpenProtocol (\r
- AllHandles[LoopIndex],\r
- &gEfiDevicePathProtocolGuid,\r
- (VOID **) &DevicePath,\r
- gImageHandle,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- // Check if it is a sub-device of the flash device\r
- if (!CompareMem (DevicePath, FlashDevicePath, FLASH_DEVICE_PATH_SIZE (FlashDevicePath))) {\r
- // Device path starts with path of flash device. Check it isn't the flash\r
- // device itself.\r
- NextNode = NextDevicePathNode (DevicePath);\r
- if (IsDevicePathEndType (NextNode)) {\r
- continue;\r
- }\r
-\r
- // Assert that this device path node represents a partition.\r
- ASSERT (NextNode->Type == MEDIA_DEVICE_PATH &&\r
- NextNode->SubType == MEDIA_HARDDRIVE_DP);\r
-\r
- PartitionNode = (HARDDRIVE_DEVICE_PATH *) NextNode;\r
-\r
- // Assert that the partition type is GPT. ReadPartitionEntries checks for\r
- // presence of a GPT, so we should never find MBR partitions.\r
- // ("MBRType" is a misnomer - this field is actually called "Partition\r
- // Format")\r
- ASSERT (PartitionNode->MBRType == MBR_TYPE_EFI_PARTITION_TABLE_HEADER);\r
-\r
- // The firmware may install a handle for "partition 0", representing the\r
- // whole device. Ignore it.\r
- if (PartitionNode->PartitionNumber == 0) {\r
- continue;\r
- }\r
-\r
- //\r
- // Add the partition handle to the list\r
- //\r
-\r
- // Create entry\r
- Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));\r
- if (Entry == NULL) {\r
- Status = EFI_OUT_OF_RESOURCES;\r
- FreePartitionList ();\r
- goto Exit;\r
- }\r
-\r
- // Copy handle and partition name\r
- Entry->PartitionHandle = AllHandles[LoopIndex];\r
- CopyMem (\r
- Entry->PartitionName,\r
- PartitionEntries[PartitionNode->PartitionNumber - 1].PartitionName, // Partition numbers start from 1.\r
- PARTITION_NAME_MAX_LENGTH\r
- );\r
- InsertTailList (&mPartitionListHead, &Entry->Link);\r
-\r
- // Print a debug message if the partition label is empty or looks like\r
- // garbage.\r
- if (!IS_ALPHA (Entry->PartitionName[0])) {\r
- DEBUG ((EFI_D_ERROR,\r
- "Warning: Partition %d doesn't seem to have a GPT partition label. "\r
- "You won't be able to flash it with Fastboot.\n",\r
- PartitionNode->PartitionNumber\r
- ));\r
- }\r
- }\r
- }\r
-\r
-Exit:\r
- FreePool (PartitionEntries);\r
- FreePool (FlashDevicePath);\r
- FreePool (AllHandles);\r
- return Status;\r
-\r
-}\r
-\r
-/*\r
- To be called when Fastboot is finished and we aren't rebooting or booting an\r
- image. Undo initialisation, free resrouces.\r
-*/\r
-STATIC\r
-VOID\r
-ArmFastbootPlatformUnInit (\r
- VOID\r
- )\r
-{\r
- FreePartitionList ();\r
-}\r
-\r
-/*\r
- Flash the partition named (according to a platform-specific scheme)\r
- PartitionName, with the image pointed to by Buffer, whose size is BufferSize.\r
-\r
- @param[in] PartitionName Null-terminated name of partition to write.\r
- @param[in] BufferSize Size of Buffer in byets.\r
- @param[in] Buffer Data to write to partition.\r
-\r
- @retval EFI_NOT_FOUND No such partition.\r
- @retval EFI_DEVICE_ERROR Flashing failed.\r
-*/\r
-STATIC\r
-EFI_STATUS\r
-ArmFastbootPlatformFlashPartition (\r
- IN CHAR8 *PartitionName,\r
- IN UINTN Size,\r
- IN VOID *Image\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_BLOCK_IO_PROTOCOL *BlockIo;\r
- EFI_DISK_IO_PROTOCOL *DiskIo;\r
- UINT32 MediaId;\r
- UINTN PartitionSize;\r
- FASTBOOT_PARTITION_LIST *Entry;\r
- CHAR16 PartitionNameUnicode[60];\r
- BOOLEAN PartitionFound;\r
-\r
- AsciiStrToUnicodeStrS (PartitionName, PartitionNameUnicode,\r
- ARRAY_SIZE (PartitionNameUnicode));\r
-\r
- PartitionFound = FALSE;\r
- Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));\r
- while (!IsNull (&mPartitionListHead, &Entry->Link)) {\r
- // Search the partition list for the partition named by PartitionName\r
- if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {\r
- PartitionFound = TRUE;\r
- break;\r
- }\r
-\r
- Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);\r
- }\r
- if (!PartitionFound) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- Status = gBS->OpenProtocol (\r
- Entry->PartitionHandle,\r
- &gEfiBlockIoProtocolGuid,\r
- (VOID **) &BlockIo,\r
- gImageHandle,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for flash: %r\n", Status));\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- // Check image will fit on device\r
- PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;\r
- if (PartitionSize < Size) {\r
- DEBUG ((EFI_D_ERROR, "Partition not big enough.\n"));\r
- DEBUG ((EFI_D_ERROR, "Partition Size:\t%d\nImage Size:\t%d\n", PartitionSize, Size));\r
-\r
- return EFI_VOLUME_FULL;\r
- }\r
-\r
- MediaId = BlockIo->Media->MediaId;\r
-\r
- Status = gBS->OpenProtocol (\r
- Entry->PartitionHandle,\r
- &gEfiDiskIoProtocolGuid,\r
- (VOID **) &DiskIo,\r
- gImageHandle,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Status = DiskIo->WriteDisk (DiskIo, MediaId, 0, Size, Image);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- BlockIo->FlushBlocks(BlockIo);\r
-\r
- return Status;\r
-}\r
-\r
-/*\r
- Erase the partition named PartitionName.\r
-\r
- @param[in] PartitionName Null-terminated name of partition to erase.\r
-\r
- @retval EFI_NOT_FOUND No such partition.\r
- @retval EFI_DEVICE_ERROR Erasing failed.\r
-*/\r
-STATIC\r
-EFI_STATUS\r
-ArmFastbootPlatformErasePartition (\r
- IN CHAR8 *Partition\r
- )\r
-{\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/*\r
- If the variable referred to by Name exists, copy it (as a null-terminated\r
- string) into Value. If it doesn't exist, put the Empty string in Value.\r
-\r
- Variable names and values may not be larger than 60 bytes, excluding the\r
- terminal null character. This is a limitation of the Fastboot protocol.\r
-\r
- The Fastboot application will handle platform-nonspecific variables\r
- (Currently "version" is the only one of these.)\r
-\r
- @param[in] Name Null-terminated name of Fastboot variable to retrieve.\r
- @param[out] Value Caller-allocated buffer for null-terminated value of\r
- variable.\r
-\r
- @retval EFI_SUCCESS The variable was retrieved, or it doesn't exist.\r
- @retval EFI_DEVICE_ERROR There was an error looking up the variable. This\r
- does _not_ include the variable not existing.\r
-*/\r
-STATIC\r
-EFI_STATUS\r
-ArmFastbootPlatformGetVar (\r
- IN CHAR8 *Name,\r
- OUT CHAR8 *Value\r
- )\r
-{\r
- if (AsciiStrCmp (Name, "product")) {\r
- AsciiStrCpyS (Value, 61, FixedPcdGetPtr (PcdFirmwareVendor));\r
- } else {\r
- *Value = '\0';\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/*\r
- React to an OEM-specific command.\r
-\r
- Future versions of this function might want to allow the platform to do some\r
- extra communication with the host. A way to do this would be to add a function\r
- to the FASTBOOT_TRANSPORT_PROTOCOL that allows the implementation of\r
- DoOemCommand to replace the ReceiveEvent with its own, and to restore the old\r
- one when it's finished.\r
-\r
- However at the moment although the specification allows it, the AOSP fastboot\r
- host application doesn't handle receiving any data from the client, and it\r
- doesn't support a data phase for OEM commands.\r
-\r
- @param[in] Command Null-terminated command string.\r
-\r
- @retval EFI_SUCCESS The command executed successfully.\r
- @retval EFI_NOT_FOUND The command wasn't recognised.\r
- @retval EFI_DEVICE_ERROR There was an error executing the command.\r
-*/\r
-STATIC\r
-EFI_STATUS\r
-ArmFastbootPlatformOemCommand (\r
- IN CHAR8 *Command\r
- )\r
-{\r
- CHAR16 CommandUnicode[65];\r
-\r
- AsciiStrToUnicodeStrS (Command, CommandUnicode, ARRAY_SIZE (CommandUnicode));\r
-\r
- if (AsciiStrCmp (Command, "Demonstrate") == 0) {\r
- DEBUG ((EFI_D_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n"));\r
- return EFI_SUCCESS;\r
- } else {\r
- DEBUG ((EFI_D_ERROR,\r
- "VExpress: Unrecognised Fastboot OEM command: %s\n",\r
- CommandUnicode\r
- ));\r
- return EFI_NOT_FOUND;\r
- }\r
-}\r
-\r
-STATIC FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol = {\r
- ArmFastbootPlatformInit,\r
- ArmFastbootPlatformUnInit,\r
- ArmFastbootPlatformFlashPartition,\r
- ArmFastbootPlatformErasePartition,\r
- ArmFastbootPlatformGetVar,\r
- ArmFastbootPlatformOemCommand\r
-};\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-ArmAndroidFastbootPlatformEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- return gBS->InstallProtocolInterface (\r
- &ImageHandle,\r
- &gAndroidFastbootPlatformProtocolGuid,\r
- EFI_NATIVE_INTERFACE,\r
- &mPlatformProtocol\r
- );\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVExpressFastBootDxe\r
- FILE_GUID = 4004e454-89a0-11e3-89aa-97ef9d942abc\r
- MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.0\r
- ENTRY_POINT = ArmAndroidFastbootPlatformEntryPoint\r
-\r
-[Sources.common]\r
- ArmVExpressFastBoot.c\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- BaseMemoryLib\r
- DebugLib\r
- DevicePathLib\r
- MemoryAllocationLib\r
- PcdLib\r
- UefiBootServicesTableLib\r
- UefiDriverEntryPoint\r
-\r
-[Protocols]\r
- gAndroidFastbootPlatformProtocolGuid\r
- gEfiBlockIoProtocolGuid\r
- gEfiDiskIoProtocolGuid\r
-\r
-[Packages]\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
- ArmPkg/ArmPkg.dec\r
-\r
-[Pcd]\r
- gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor\r
+++ /dev/null
-#/** @file\r
-# Arm Versatile Express package.\r
-#\r
-# Copyright (c) 2012-2015, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials are licensed and made available\r
-# under the terms and conditions of the BSD License which accompanies this\r
-# distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- DEC_SPECIFICATION = 0x00010005\r
- PACKAGE_NAME = ArmVExpressPkg\r
- PACKAGE_GUID = 9c0aaed4-74c5-4043-b417-a3223814ce76\r
- PACKAGE_VERSION = 0.1\r
-\r
-################################################################################\r
-#\r
-# Include Section - list of Include Paths that are provided by this package.\r
-# Comments are used for Keywords and Module Types.\r
-#\r
-# Supported Module Types:\r
-# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-#\r
-################################################################################\r
-[Includes.common]\r
- Include # Root include for the package\r
-\r
-[Guids.common]\r
- gArmVExpressTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
-\r
-[PcdsFeatureFlag.common]\r
-\r
-[PcdsFixedAtBuild.common]\r
- #\r
- # MaxMode must be one number higher than the actual max mode,\r
- # i.e. for actual maximum mode 2, set the value to 3.\r
- #\r
- # For a list of mode numbers look in LcdArmVExpress.c\r
- #\r
- gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000001\r
- gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000002\r
- gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000003\r
-\r
- #\r
- # Device path of block device on which Fastboot will flash partitions\r
- #\r
- gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|""|VOID*|0x00000004\r
+++ /dev/null
-/** @file\r
-* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
-*\r
-* Copyright (c) 2012, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __ARM_VEXPRESS_CTA15A7_H__\r
-#define __ARM_VEXPRESS_CTA15A7_H__\r
-\r
-#include <VExpressMotherBoard.h>\r
-\r
-/***********************************************************************************\r
-// Platform Memory Map\r
-************************************************************************************/\r
-\r
-// Motherboard Peripheral and On-chip peripheral\r
-#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r
-\r
-#ifdef ARM_BIGLITTLE_TC2\r
-\r
-// Secure NOR Flash\r
-#define ARM_VE_SEC_NOR0_BASE 0x00000000\r
-#define ARM_VE_SEC_NOR0_SZ SIZE_64MB\r
-\r
-// Secure RAM\r
-#define ARM_VE_SEC_RAM0_BASE 0x04000000\r
-#define ARM_VE_SEC_RAM0_SZ SIZE_64MB\r
-\r
-#endif\r
-\r
-// NOR Flash 0\r
-#define ARM_VE_SMB_NOR0_BASE 0x08000000\r
-#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
-// NOR Flash 1\r
-#define ARM_VE_SMB_NOR1_BASE 0x0C000000\r
-#define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r
-\r
-// SRAM\r
-#define ARM_VE_SMB_SRAM_BASE 0x14000000\r
-#define ARM_VE_SMB_SRAM_SZ SIZE_32MB\r
-\r
-// USB, Ethernet, VRAM\r
-#ifdef ARM_BIGLITTLE_TC2\r
-#define ARM_VE_SMB_PERIPH_BASE 0x18000000\r
-#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)\r
-#else\r
-#define ARM_VE_SMB_PERIPH_BASE 0x1C000000\r
-#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)\r
-#endif\r
-#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE\r
-\r
-// On-Chip non-secure ROM\r
-#ifdef ARM_BIGLITTLE_TC2\r
-#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000\r
-#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB\r
-#endif\r
-\r
-// On-Chip Peripherals\r
-#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000\r
-#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000\r
-\r
-// On-Chip non-secure SRAM\r
-#ifdef ARM_BIGLITTLE_TC2\r
-#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000\r
-#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB\r
-#endif\r
-\r
-// Allocate a section for the VRAM (Video RAM)\r
-// If 0 then allow random memory allocation\r
-#define LCD_VRAM_CORE_TILE_BASE 0\r
-\r
-// Define SEC phase sync point\r
-#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)\r
-\r
-/***********************************************************************************\r
- Core Tile memory-mapped Peripherals\r
-************************************************************************************/\r
-\r
-// PL354 Static Memory Controller Base\r
-#ifdef ARM_BIGLITTLE_TC2\r
-#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000\r
-#else\r
-#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
-#endif\r
-\r
-#define ARM_CTA15A7_SCC_BASE 0x7FFF0000\r
-#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)\r
-\r
-#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48\r
-\r
-#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)\r
-#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)\r
-#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)\r
-#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)\r
-#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4)\r
-\r
-#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)\r
-#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)\r
-#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)\r
-#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)\r
-#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)\r
-#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)\r
-#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)\r
-#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)\r
-#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)\r
-\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)\r
-#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)\r
-\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)\r
-#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)\r
-\r
-\r
-/***********************************************************************************\r
-// Memory-mapped peripherals\r
-************************************************************************************/\r
-\r
-/*// SP810 Controller\r
-#undef SP810_CTRL_BASE\r
-#define SP810_CTRL_BASE 0x1C020000\r
-\r
-// PL111 Colour LCD Controller\r
-#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE\r
-#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r
-#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
-\r
-// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
-#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
-* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __ARM_VEXPRESS_H__\r
-#define __ARM_VEXPRESS_H__\r
-\r
-#include <VExpressMotherBoard.h>\r
-\r
-/***********************************************************************************\r
-// Platform Memory Map\r
-************************************************************************************/\r
-\r
-// Can be NOR0, NOR1, DRAM\r
-#define ARM_VE_REMAP_BASE 0x00000000\r
-#define ARM_VE_REMAP_SZ SIZE_64MB\r
-\r
-// Motherboard Peripheral and On-chip peripheral\r
-#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r
-\r
-// NOR Flash 1\r
-// There is typo in the reference manual for the Base address of NOR Flash 1\r
-#define ARM_VE_SMB_NOR0_BASE 0x08000000\r
-#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
-// NOR Flash 2\r
-#define ARM_VE_SMB_NOR1_BASE 0x0C000000\r
-#define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r
-// SRAM\r
-#define ARM_VE_SMB_SRAM_BASE 0x2E000000\r
-#define ARM_VE_SMB_SRAM_SZ SIZE_64KB\r
-// USB, Ethernet, VRAM\r
-#define ARM_VE_SMB_PERIPH_BASE 0x18800000\r
-#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB)\r
-\r
-#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000\r
-#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000\r
-\r
-// DRAM\r
-#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)\r
-#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)\r
-\r
-// This can be any value since we only support motherboard PL111\r
-#define LCD_VRAM_CORE_TILE_BASE 0x00000000\r
-\r
-// On-chip peripherals (Snoop Control Unit etc...)\r
-#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000\r
-// Note: The TRM says not all the peripherals are implemented\r
-#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB\r
-\r
-\r
-// External AXI between daughterboards (Logic Tile)\r
-#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled\r
-#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */\r
-\r
-/***********************************************************************************\r
-// Memory-mapped peripherals\r
-************************************************************************************/\r
-\r
-// SP810 Controller\r
-#undef SP810_CTRL_BASE\r
-#define SP810_CTRL_BASE 0x1C020000\r
-\r
-// PL111 Colour LCD Controller\r
-#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE\r
-#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r
-#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
-* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
-*\r
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __VEXPRESSMOTHERBOARD_H_\r
-#define __VEXPRESSMOTHERBOARD_H_\r
-\r
-#include <ArmPlatform.h>\r
-\r
-/***********************************************************************************\r
-// Motherboard memory-mapped peripherals\r
-************************************************************************************/\r
-\r
-// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
-#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)\r
-#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)\r
-#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r
-#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
-#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
-#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r
-#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)\r
-#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)\r
-#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
-#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
-#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
-#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
-#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
-\r
-// SP810 Controller\r
-#ifndef SP810_CTRL_BASE\r
-#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
-#endif\r
-\r
-// PL111 Colour LCD Controller - motherboard\r
-#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r
-#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r
-\r
-// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
-#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r
-\r
-#define ARM_VE_SYS_PROC_ID_HBI 0xFFF\r
-#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)\r
-#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A7 (UINT32)(0x18U << 24)\r
-#define ARM_VE_SYS_PROC_ID_CORTEX_A12 (UINT32)(0x1CU << 24)\r
-\r
-// Boot Master Select:\r
-// 0 = Site 1 boot master\r
-// 1 = Site 2 boot master\r
-#define ARM_VE_SYS_MISC_MASTERSITE (1 << 14)\r
-//\r
-// Sites where the peripheral is fitted\r
-//\r
-#define ARM_VE_UNSUPPORTED ~0\r
-#define ARM_VE_MOTHERBOARD_SITE 0\r
-#define ARM_VE_DAUGHTERBOARD_1_SITE 1\r
-#define ARM_VE_DAUGHTERBOARD_2_SITE 2\r
-\r
-#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))\r
-\r
-//\r
-// System Configuration Control Functions\r
-//\r
-#define SYS_CFG_OSC 1\r
-#define SYS_CFG_VOLT 2\r
-#define SYS_CFG_AMP 3\r
-#define SYS_CFG_TEMP 4\r
-#define SYS_CFG_RESET 5\r
-#define SYS_CFG_SCC 6\r
-#define SYS_CFG_MUXFPGA 7\r
-#define SYS_CFG_SHUTDOWN 8\r
-#define SYS_CFG_REBOOT 9\r
-#define SYS_CFG_DVIMODE 11\r
-#define SYS_CFG_POWER 12\r
-// Oscillator for Site 1\r
-#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)\r
-// Oscillator for Site 2\r
-#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)\r
-// Can not access the battery backed-up hardware clock on the Versatile Express motherboard\r
-#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)\r
-\r
-//\r
-// System ID\r
-//\r
-// All RTSM VE models have the same System ID : 0x225F500\r
-//\r
-// FVP models have a different System ID.\r
-// Default Base model System ID : 0x00201100\r
-// [31:28] Rev - Board revision: 0x0 = Rev A\r
-// [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform\r
-// [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)\r
-// [11:8] Plat - Platform type: 0x1 = Model\r
-// [7:0] FPGA - FPGA build, BCD coded: 0x00\r
-//\r
-//HBI = 010 = Foundation Model\r
-//HBI = 020 = Base Platform\r
-//\r
-// And specifically, the GIC register banks start at the following\r
-// addresses:\r
-// Variant = 0 Variant = 1\r
-//GICD 0x2c001000 0x2f000000\r
-//GICC 0x2c002000 0x2c000000\r
-//GICH 0x2c004000 0x2c010000\r
-//GICV 0x2c006000 0x2c020000\r
-\r
-#define ARM_FVP_BASE_BOARD_SYS_ID (0x00200100)\r
-#define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)\r
-\r
-#define ARM_FVP_SYS_ID_REV_MASK (UINT32)(0xFUL << 28)\r
-#define ARM_FVP_SYS_ID_HBI_MASK (UINT32)(0xFFFUL << 16)\r
-#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)\r
-#define ARM_FVP_SYS_ID_PLAT_MASK (UINT32)(0xFUL << 8 )\r
-#define ARM_FVP_SYS_ID_FPGA_MASK (UINT32)(0xFFUL << 0 )\r
-#define ARM_FVP_GIC_VE_MMAP 0x0\r
-#define ARM_FVP_GIC_BASE_MMAP (UINT32)(1 << 12)\r
-\r
-// The default SYS_IDs. These can be changed when starting the model.\r
-#define ARM_RTSM_SYS_ID (0x225F500)\r
-#define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)\r
-#define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)\r
-\r
-#endif /* VEXPRESSMOTHERBOARD_H_ */\r
+++ /dev/null
-#/* @file\r
-#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = CTA15A7ArmVExpressLib\r
- FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- MemoryAllocationLib\r
- SerialPortLib\r
-\r
-[Sources.common]\r
- CTA15-A7.c\r
- CTA15-A7Mem.c\r
- CTA15-A7Helper.asm | RVCT\r
- CTA15-A7Helper.S | GCC\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
-\r
-[FixedPcd]\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
-\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Ppi/ArmMpCoreInfo.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {\r
- {\r
- // Cluster 0, Core 0\r
- 0x0, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,\r
- (UINT64)0\r
- },\r
- {\r
- // Cluster 0, Core 1\r
- 0x0, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,\r
- (UINT64)0\r
- },\r
-#ifndef ARM_BIGLITTLE_TC2\r
- {\r
- // Cluster 0, Core 2\r
- 0x0, 0x2,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,\r
- (UINT64)0\r
- },\r
- {\r
- // Cluster 0, Core 3\r
- 0x0, 0x3,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,\r
- (UINT64)0\r
- },\r
-#endif\r
- {\r
- // Cluster 1, Core 0\r
- 0x1, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,\r
- (UINT64)0\r
- },\r
- {\r
- // Cluster 1, Core 1\r
- 0x1, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,\r
- (UINT64)0\r
- },\r
- {\r
- // Cluster 1, Core 2\r
- 0x1, 0x2,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,\r
- (UINT64)0\r
- }\r
-#ifndef ARM_BIGLITTLE_TC2\r
- ,{\r
- // Cluster 1, Core 3\r
- 0x1, 0x3,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
- (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,\r
- (UINT64)0\r
- }\r
-#endif\r
-};\r
-\r
-/**\r
- Return the current Boot Mode\r
-\r
- This function returns the boot reason on the platform\r
-\r
- @return Return the current Boot Mode of the platform\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-ArmPlatformGetBootMode (\r
- VOID\r
- )\r
-{\r
- if (MmioRead32(ARM_CTA15A7_SCC_SYSINFO) & ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH) {\r
- return BOOT_WITH_DEFAULT_SETTINGS;\r
- } else {\r
- return BOOT_WITH_FULL_CONFIGURATION;\r
- }\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup in the normal world\r
-\r
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
- in the PEI phase.\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return RETURN_SUCCESS;\r
- }\r
-\r
- // Nothing to do here\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PrePeiCoreGetMpCoreInfo (\r
- OUT UINTN *CoreCount,\r
- OUT ARM_CORE_INFO **ArmCoreTable\r
- )\r
-{\r
- // Only support one cluster\r
- *CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);\r
- *ArmCoreTable = mVersatileExpressCTA15A7InfoTable;\r
- return EFI_SUCCESS;\r
-}\r
-\r
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
-\r
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
- {\r
- EFI_PEI_PPI_DESCRIPTOR_PPI,\r
- &gArmMpCoreInfoPpiGuid,\r
- &mMpCoreInfoPpi\r
- }\r
-};\r
-\r
-VOID\r
-ArmPlatformGetPlatformPpiList (\r
- OUT UINTN *PpiListSize,\r
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
- )\r
-{\r
- *PpiListSize = sizeof(gPlatformPpiTable);\r
- *PpiList = gPlatformPpiTable;\r
-}\r
+++ /dev/null
-//\r
-// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmLib.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-ASM_FUNC(ArmPlatformPeiBootAction)\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformGetCorePosition)\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #7\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformIsPrimaryCore)\r
- // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
- // with cpu_id[0:3] and cluster_id[4:7]\r
- MOV32 (r1, ARM_CTA15A7_SCC_CFGREG48)\r
- ldr r1, [r1]\r
- lsr r1, #24\r
-\r
- // Shift the SCC value to get the cluster ID at the offset #8\r
- lsl r2, r1, #4\r
- and r2, r2, #0xF00\r
-\r
- // Keep only the cpu ID from the original SCC\r
- and r1, r1, #0x0F\r
- // Add the Cluster ID to the Cpu ID\r
- orr r1, r1, r2\r
-\r
- // Keep the Cluster ID and Core ID from the MPID\r
- MOV32 (r2, ARM_CLUSTER_MASK | ARM_CORE_MASK)\r
- and r0, r0, r2\r
-\r
- // Compare mpid and boot cpu from ARM_SCC_CFGREG48\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
- // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
- // with cpu_id[0:3] and cluster_id[4:7]\r
- MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48)\r
- ldr r0, [r0]\r
- lsr r0, #24\r
-\r
- // Shift the SCC value to get the cluster ID at the offset #8\r
- lsl r1, r0, #4\r
- and r1, r1, #0xF00\r
-\r
- // Keep only the cpu ID from the original SCC\r
- and r0, r0, #0x0F\r
- // Add the Cluster ID to the Cpu ID\r
- orr r0, r0, r1\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Library/ArmLib.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformPeiBootAction\r
- EXPORT ArmPlatformGetCorePosition\r
- EXPORT ArmPlatformIsPrimaryCore\r
- EXPORT ArmPlatformGetPrimaryCoreMpId\r
-\r
- PRESERVE8\r
- AREA CTA15A7Helper, CODE, READONLY\r
-\r
-ArmPlatformPeiBootAction FUNCTION\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformGetCorePosition FUNCTION\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #7\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformIsPrimaryCore FUNCTION\r
- // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
- // with cpu_id[0:3] and cluster_id[4:7]\r
- mov32 r1, ARM_CTA15A7_SCC_CFGREG48\r
- ldr r1, [r1]\r
- lsr r1, #24\r
-\r
- // Shift the SCC value to get the cluster ID at the offset #8\r
- lsl r2, r1, #4\r
- and r2, r2, #0xF00\r
-\r
- // Keep only the cpu ID from the original SCC\r
- and r1, r1, #0x0F\r
- // Add the Cluster ID to the Cpu ID\r
- orr r1, r1, r2\r
-\r
- // Keep the Cluster ID and Core ID from the MPID\r
- mov32 r2, ARM_CLUSTER_MASK :OR: ARM_CORE_MASK\r
- and r0, r0, r2\r
-\r
- // Compare mpid and boot cpu from ARM_SCC_CFGREG48\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
- // with cpu_id[0:3] and cluster_id[4:7]\r
- mov32 r0, ARM_CTA15A7_SCC_CFGREG48\r
- ldr r0, [r0]\r
- lsr r0, #24\r
-\r
- // Shift the SCC value to get the cluster ID at the offset #8\r
- lsl r1, r0, #4\r
- and r1, r1, #0xF00\r
-\r
- // Keep only the cpu ID from the original SCC\r
- and r0, r0, #0x0F\r
- // Add the Cluster ID to the Cpu ID\r
- orr r0, r0, r1\r
- bx lr\r
- ENDFUNC\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2012, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-/**\r
- Return the Virtual Memory Map of your platform\r
-\r
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
-\r
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
- Virtual Memory mapping. This array must be ended by a zero-filled\r
- entry\r
-\r
-**/\r
-VOID\r
-ArmPlatformGetVirtualMemoryMap (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
- )\r
-{\r
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT (VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
- CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
- } else {\r
- CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
- }\r
-\r
-#ifdef ARM_BIGLITTLE_TC2\r
- // Secure NOR0 Flash\r
- VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
- // Secure RAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-#endif\r
-\r
- // SMB CS0 - NOR0 Flash\r
- VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
- // Environment Variables region\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
- VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SMB CS1 or CS4 - NOR1 Flash\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;\r
- VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
- // Environment Variables region\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);\r
- VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SMB CS3 or CS1 - PSRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // Motherboard peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
-#ifdef ARM_BIGLITTLE_TC2\r
- // Non-secure ROM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-#endif\r
-\r
- // OnChip peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SCC Region\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;\r
- VirtualMemoryTable[Index].Length = SIZE_64KB;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
-#ifdef ARM_BIGLITTLE_TC2\r
- // TC2 OnChip non-secure SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-#endif\r
-\r
-#ifndef ARM_BIGLITTLE_TC2\r
- // Workaround for SRAM bug in RTSM\r
- if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {\r
- VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;\r
- VirtualMemoryTable[Index].VirtualBase = 0x80000000;\r
- VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
- }\r
-#endif\r
-\r
- // DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // Detect if it is a 1GB or 2GB Test Chip\r
- // [16:19]: 0=1GB TC2, 1=2GB TC2\r
- if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {\r
- DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),\r
- SIZE_1GB\r
- );\r
-\r
- // Map the additional 1GB into the MMU\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);\r
- VirtualMemoryTable[Index].Length = SIZE_1GB;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
- }\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
-}\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Library/ArmLib.h>\r
-\r
-ASM_FUNC(ArmPlatformPeiBootAction)\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
- MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))\r
- ret\r
-\r
-# IN None\r
-# OUT x0 = number of cores present in the system\r
-ASM_FUNC(ArmGetCpuCountPerCluster)\r
- MOV32 (w0, FixedPcdGet32 (PcdCoreCount))\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformIsPrimaryCore)\r
- MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
- and x0, x0, x1\r
- MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))\r
- cmp w0, w1\r
- b.ne 1f\r
- mov x0, #1\r
- ret\r
-1:\r
- mov x0, #0\r
- ret\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-// With this function: CorePos = (ClusterId * 4) + CoreId\r
-ASM_FUNC(ArmPlatformGetCorePosition)\r
- and x1, x0, #ARM_CORE_MASK\r
- and x0, x0, #ARM_CLUSTER_MASK\r
- add x0, x1, x0, LSR #6\r
- ret\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmLib.h>\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-ASM_FUNC(ArmPlatformPeiBootAction)\r
- bx lr\r
-\r
-# IN None\r
-# OUT r0 = SCU Base Address\r
-ASM_FUNC(ArmGetScuBaseAddress)\r
- # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- # offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
- MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))\r
- bx lr\r
-\r
-# IN None\r
-# OUT r0 = number of cores present in the system\r
-ASM_FUNC(ArmGetCpuCountPerCluster)\r
- stmfd SP!, {r1-r2}\r
-\r
- # Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- # Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- MOV32 (r0, ARM_CPU_TYPE_MASK)\r
- and r1, r1, r0\r
-\r
- MOV32 (r0, ARM_CPU_TYPE_A15)\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15:\r
- mov r2, lr @ Save link register\r
- bl ArmGetScuBaseAddress @ Read SCU Base Address\r
- mov lr, r2 @ Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg:\r
- mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-_Return:\r
- and r0, r0, #3\r
- # Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformIsPrimaryCore)\r
- MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
- and r0, r0, r1\r
- MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformGetCorePosition)\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #7\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformPeiBootAction\r
- EXPORT ArmGetCpuCountPerCluster\r
- EXPORT ArmPlatformIsPrimaryCore\r
- EXPORT ArmPlatformGetPrimaryCoreMpId\r
- EXPORT ArmPlatformGetCorePosition\r
-\r
- AREA RTSMHelper, CODE, READONLY\r
-\r
-ArmPlatformPeiBootAction FUNCTION\r
- bx lr\r
- ENDFUNC\r
-\r
-// IN None\r
-// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress FUNCTION\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)\r
- bx lr\r
- ENDFUNC\r
-\r
-// IN None\r
-// OUT r0 = number of cores present in the system\r
-ArmGetCpuCountPerCluster FUNCTION\r
- stmfd SP!, {r1-r2}\r
-\r
- // Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- // Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- mov r0, #ARM_CPU_TYPE_MASK\r
- and r1, r1, r0\r
-\r
- mov r0, #ARM_CPU_TYPE_A15\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15\r
- mov r2, lr ; Save link register\r
- bl ArmGetScuBaseAddress ; Read SCU Base Address\r
- mov lr, r2 ; Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg\r
- mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-\r
-_Return\r
- and r0, r0, #3\r
- // Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformIsPrimaryCore FUNCTION\r
- mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)\r
- and r0, r0, r1\r
- mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)\r
- ldr r1, [r1]\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformGetCorePosition FUNCTION\r
- and r1, r0, #ARM_CORE_MASK\r
- and r0, r0, #ARM_CLUSTER_MASK\r
- add r0, r1, r0, LSR #7\r
- bx lr\r
- ENDFUNC\r
-\r
- END\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = RTSMArmVExpressLib\r
- FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- MemoryAllocationLib\r
- SerialPortLib\r
- HobLib\r
-\r
-[Sources.common]\r
- RTSM.c\r
- RTSMMem.c\r
-\r
-[Sources.ARM]\r
- Arm/RTSMHelper.asm | RVCT\r
- Arm/RTSMHelper.S | GCC\r
-\r
-[Sources.AARCH64]\r
- AArch64/RTSMHelper.S\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = RTSMArmVExpressLibSec\r
- FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- SerialPortLib\r
-\r
-[Sources.common]\r
- RTSM.c\r
-\r
-[Sources.ARM]\r
- Arm/RTSMHelper.asm | RVCT\r
- Arm/RTSMHelper.S | GCC\r
-\r
-[Sources.AARCH64]\r
- AArch64/RTSMHelper.S\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Ppi/ArmMpCoreInfo.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-/**\r
- Return the core per cluster. The method may differ per core type\r
-\r
- This function might be called from assembler before any stack is set.\r
-\r
- @return Return the core count per cluster\r
-\r
-**/\r
-UINTN\r
-ArmGetCpuCountPerCluster (\r
- VOID\r
- );\r
-\r
-ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {\r
- {\r
- // Cluster 0, Core 0\r
- 0x0, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 1\r
- 0x0, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 2\r
- 0x0, 0x2,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 3\r
- 0x0, 0x3,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 0\r
- 0x1, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 1\r
- 0x1, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 2\r
- 0x1, 0x2,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 1, Core 3\r
- 0x1, 0x3,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- }\r
-};\r
-\r
-/**\r
- Return the current Boot Mode\r
-\r
- This function returns the boot reason on the platform\r
-\r
- @return Return the current Boot Mode of the platform\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-ArmPlatformGetBootMode (\r
- VOID\r
- )\r
-{\r
- return BOOT_WITH_FULL_CONFIGURATION;\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup in the normal world\r
-\r
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
- in the PEI phase.\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return RETURN_SUCCESS;\r
- }\r
-\r
- // Disable memory remapping and return to normal mapping\r
- MmioOr32 (SP810_CTRL_BASE, BIT8);\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PrePeiCoreGetMpCoreInfo (\r
- OUT UINTN *CoreCount,\r
- OUT ARM_CORE_INFO **ArmCoreTable\r
- )\r
-{\r
- UINT32 ProcType;\r
-\r
- ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;\r
- if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {\r
- // Only support one cluster on all but ARMv8 FVP platform. FVP still uses CortexA9 ID.\r
- *CoreCount = ArmGetCpuCountPerCluster ();\r
- *ArmCoreTable = mVersatileExpressMpCoreInfoTable;\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_UNSUPPORTED;\r
- }\r
-}\r
-\r
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
-\r
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
- {\r
- EFI_PEI_PPI_DESCRIPTOR_PPI,\r
- &gArmMpCoreInfoPpiGuid,\r
- &mMpCoreInfoPpi\r
- }\r
-};\r
-\r
-VOID\r
-ArmPlatformGetPlatformPpiList (\r
- OUT UINTN *PpiListSize,\r
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
- )\r
-{\r
- *PpiListSize = sizeof(gPlatformPpiTable);\r
- *PpiList = gPlatformPpiTable;\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/HobLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <ArmPlatform.h>\r
-\r
-// Number of Virtual Memory Map Descriptors\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-/**\r
- Return the Virtual Memory Map of your platform\r
-\r
- This Virtual Memory Map is used by MemoryInitPei Module to initialize\r
- the MMU on your platform.\r
-\r
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR\r
- describing a Physical-to-Virtual Memory\r
- mapping. This array must be ended by a\r
- zero-filled entry.\r
-\r
-**/\r
-VOID\r
-ArmPlatformGetVirtualMemoryMap (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
- )\r
-{\r
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
- UINT32 SysId;\r
- BOOLEAN HasSparseMemory;\r
- EFI_VIRTUAL_ADDRESS SparseMemoryBase;\r
- UINT64 SparseMemorySize;\r
-\r
- ASSERT (VirtualMemoryMap != NULL);\r
-\r
- // The FVP model has Sparse memory\r
- SysId = MmioRead32 (ARM_VE_SYS_ID_REG);\r
- if (SysId != ARM_RTSM_SYS_ID) {\r
- HasSparseMemory = TRUE;\r
-\r
- ResourceAttributes =\r
- EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
- EFI_RESOURCE_ATTRIBUTE_TESTED;\r
-\r
- // Declared the additional DRAM from 2GB to 4GB\r
- SparseMemoryBase = 0x0880000000;\r
- SparseMemorySize = SIZE_2GB;\r
-\r
- BuildResourceDescriptorHob (\r
- EFI_RESOURCE_SYSTEM_MEMORY,\r
- ResourceAttributes,\r
- SparseMemoryBase,\r
- SparseMemorySize);\r
- } else {\r
- HasSparseMemory = FALSE;\r
- SparseMemoryBase = 0x0;\r
- SparseMemorySize = 0x0;\r
- }\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)\r
- AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)\r
- * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- CacheAttributes = (FeaturePcdGet(PcdCacheEnable))\r
- ? DDR_ATTRIBUTES_CACHED\r
- : DDR_ATTRIBUTES_UNCACHED;\r
-\r
- // ReMap (Either NOR Flash or DRAM)\r
- VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // CPU peripherals. TRM. Manual says not all of them are implemented.\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SMB CS0-CS1 - NOR Flash 1 & 2\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // SMB CS2 - SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // Peripheral CS2 and CS3\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // VRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
- VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;\r
- //\r
- // Map the VRAM region as Normal Non-Cacheable memory and not device memory,\r
- // so that we can use the accelerated string routines that may use unaligned\r
- // accesses or DC ZVA instructions. The enum identifier is slightly awkward\r
- // here, but it maps to a memory type that allows buffering and reordering.\r
- //\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
-\r
- // Map sparse memory region if present\r
- if (HasSparseMemory) {\r
- VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r
- VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;\r
- VirtualMemoryTable[Index].Length = SparseMemorySize;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
- }\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
-}\r
+++ /dev/null
-/** @file ArmVExpressSysConfig.c\r
-\r
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#include <Library/ArmPlatformSysConfigLib.h>\r
-#include <ArmPlatform.h>\r
-\r
-//\r
-// SYS_CFGCTRL Bits\r
-//\r
-#define SYS_CFGCTRL_START BIT31\r
-#define SYS_CFGCTRL_READ (0 << 30)\r
-#define SYS_CFGCTRL_WRITE (1 << 30)\r
-#define SYS_CFGCTRL_FUNCTION(fun) (((fun ) & 0x3F) << 20)\r
-#define SYS_CFGCTRL_SITE(site) (((site) & 0x3) << 16)\r
-#define SYS_CFGCTRL_POSITION(pos) (((pos ) & 0xF) << 12)\r
-#define SYS_CFGCTRL_DEVICE(dev) ((dev ) & 0xFFF)\r
-\r
-//\r
-// SYS_CFGSTAT Bits\r
-//\r
-#define SYS_CFGSTAT_ERROR BIT1\r
-#define SYS_CFGSTAT_COMPLETE BIT0\r
-\r
-/****************************************************************************\r
- *\r
- * This file makes it easier to access the System Configuration Registers\r
- * in the ARM Versatile Express motherboard.\r
- *\r
- ****************************************************************************/\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigInitialize (\r
- VOID\r
- )\r
-{\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/***************************************\r
- * GENERAL FUNCTION: AccessSysCfgRegister\r
- * Interacts with\r
- * SYS_CFGSTAT\r
- * SYS_CFGDATA\r
- * SYS_CFGCTRL\r
- * for setting and for reading out values\r
- ***************************************/\r
-\r
-RETURN_STATUS\r
-AccessSysCfgRegister (\r
- IN UINT32 ReadWrite,\r
- IN UINT32 Function,\r
- IN UINT32 Site,\r
- IN UINT32 Position,\r
- IN UINT32 Device,\r
- IN OUT UINT32* Data\r
- )\r
-{\r
- UINT32 SysCfgCtrl;\r
-\r
- // Clear the COMPLETE bit\r
- MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE);\r
-\r
- // If writing, then set the data value\r
- if(ReadWrite == SYS_CFGCTRL_WRITE) {\r
- MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data);\r
- }\r
-\r
- // Set the control value\r
- SysCfgCtrl = SYS_CFGCTRL_START | ReadWrite | SYS_CFGCTRL_FUNCTION(Function) | SYS_CFGCTRL_SITE(Site) |\r
- SYS_CFGCTRL_POSITION(Position) | SYS_CFGCTRL_DEVICE(Device);\r
- MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl);\r
-\r
- // Wait until the COMPLETE bit is set\r
- while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) == 0);\r
-\r
- // Check for errors\r
- if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) {\r
- return RETURN_DEVICE_ERROR;\r
- }\r
-\r
- // If reading then get the data value\r
- if(ReadWrite == SYS_CFGCTRL_READ) {\r
- *Data = MmioRead32(ARM_VE_SYS_CFGDATA_REG);\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigGet (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- OUT UINT32* Value\r
- )\r
-{\r
- UINT32 Site;\r
- UINT32 Position;\r
- UINT32 Device;\r
-\r
- Position = 0;\r
- Device = 0;\r
-\r
- // Intercept some functions\r
- switch(Function) {\r
-\r
- case SYS_CFG_OSC_SITE1:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_1_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC_SITE2:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_2_SITE;\r
- break;\r
-\r
- case SYS_CFG_MUXFPGA:\r
- Site = *Value;\r
- break;\r
-\r
- case SYS_CFG_OSC:\r
- case SYS_CFG_VOLT:\r
- case SYS_CFG_AMP:\r
- case SYS_CFG_TEMP:\r
- case SYS_CFG_RESET:\r
- case SYS_CFG_SCC:\r
- case SYS_CFG_DVIMODE:\r
- case SYS_CFG_POWER:\r
- Site = ARM_VE_MOTHERBOARD_SITE;\r
- break;\r
-\r
- case SYS_CFG_SHUTDOWN:\r
- case SYS_CFG_REBOOT:\r
- case SYS_CFG_RTC:\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return AccessSysCfgRegister (SYS_CFGCTRL_READ, Function, Site, Position, Device, Value);\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigGetValues (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- IN UINTN Size,\r
- OUT UINT32* Values\r
- )\r
-{\r
- return RETURN_UNSUPPORTED;\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigSet (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- IN UINT32 Value\r
- )\r
-{\r
- UINT32 Site;\r
- UINT32 Position;\r
- UINT32 Device;\r
-\r
- Position = 0;\r
- Device = 0;\r
-\r
- // Intercept some functions\r
- switch(Function) {\r
-\r
- case SYS_CFG_OSC_SITE1:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_1_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC_SITE2:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_2_SITE;\r
- break;\r
-\r
- case SYS_CFG_MUXFPGA:\r
- Site = Value;\r
- break;\r
-\r
- case SYS_CFG_RESET:\r
- case SYS_CFG_SCC:\r
- case SYS_CFG_SHUTDOWN:\r
- case SYS_CFG_REBOOT:\r
- case SYS_CFG_DVIMODE:\r
- case SYS_CFG_POWER:\r
- Site = ARM_VE_MOTHERBOARD_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC:\r
- case SYS_CFG_VOLT:\r
- case SYS_CFG_AMP:\r
- case SYS_CFG_TEMP:\r
- case SYS_CFG_RTC:\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigSetDevice (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- IN UINT32 Device,\r
- IN UINT32 Value\r
- )\r
-{\r
- UINT32 Site;\r
- UINT32 Position;\r
-\r
- Position = 0;\r
-\r
- // Intercept some functions\r
- switch(Function) {\r
- case SYS_CFG_SCC:\r
-#ifdef ARM_VE_SCC_BASE\r
- MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value);\r
- return RETURN_SUCCESS;\r
-#else\r
- // There is no System Configuration Controller on the Model\r
- return RETURN_UNSUPPORTED;\r
-#endif\r
-\r
- case SYS_CFG_OSC_SITE1:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_1_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC_SITE2:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_2_SITE;\r
- break;\r
-\r
- case SYS_CFG_MUXFPGA:\r
- Site = Value;\r
- break;\r
-\r
- case SYS_CFG_RTC:\r
- return RETURN_UNSUPPORTED;\r
- //break;\r
-\r
- case SYS_CFG_OSC:\r
- case SYS_CFG_VOLT:\r
- case SYS_CFG_AMP:\r
- case SYS_CFG_TEMP:\r
- case SYS_CFG_RESET:\r
- case SYS_CFG_SHUTDOWN:\r
- case SYS_CFG_REBOOT:\r
- case SYS_CFG_DVIMODE:\r
- case SYS_CFG_POWER:\r
- Site = ARM_VE_MOTHERBOARD_SITE;\r
- break;\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for ArmVExpressSysConfigLib module\r
-#\r
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVExpressSysConfigLib\r
- FILE_GUID = a05b5cc0-82d2-11e0-82cb-0002a5d5c51b\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformSysConfigLib|SEC DXE_DRIVER\r
-\r
-[Sources.common]\r
- ArmVExpressSysConfig.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- IoLib\r
+++ /dev/null
-/** @file ArmVExpressSysConfig.c\r
-\r
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#include <Library/ArmPlatformSysConfigLib.h>\r
-#include <ArmPlatform.h>\r
-\r
-#include <Uefi.h>\r
-#include <Library/UefiRuntimeLib.h>\r
-\r
-//\r
-// SYS_CFGCTRL Bits\r
-//\r
-#define SYS_CFGCTRL_START BIT31\r
-#define SYS_CFGCTRL_READ (0 << 30)\r
-#define SYS_CFGCTRL_WRITE (1 << 30)\r
-#define SYS_CFGCTRL_FUNCTION(fun) (((fun ) & 0x3F) << 20)\r
-#define SYS_CFGCTRL_SITE(site) (((site) & 0x3) << 16)\r
-#define SYS_CFGCTRL_POSITION(pos) (((pos ) & 0xF) << 12)\r
-#define SYS_CFGCTRL_DEVICE(dev) ((dev ) & 0xFFF)\r
-\r
-//\r
-// SYS_CFGSTAT Bits\r
-//\r
-#define SYS_CFGSTAT_ERROR BIT1\r
-#define SYS_CFGSTAT_COMPLETE BIT0\r
-\r
-/****************************************************************************\r
- *\r
- * This file makes it easier to access the System Configuration Registers\r
- * in the ARM Versatile Express motherboard.\r
- *\r
- ****************************************************************************/\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigInitialize (\r
- VOID\r
- )\r
-{\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/***************************************\r
- * GENERAL FUNCTION: AccessSysCfgRegister\r
- * Interacts with\r
- * SYS_CFGSTAT\r
- * SYS_CFGDATA\r
- * SYS_CFGCTRL\r
- * for setting and for reading out values\r
- ***************************************/\r
-\r
-RETURN_STATUS\r
-AccessSysCfgRegister (\r
- IN UINT32 ReadWrite,\r
- IN UINT32 Function,\r
- IN UINT32 Site,\r
- IN UINT32 Position,\r
- IN UINT32 Device,\r
- IN OUT UINT32* Data\r
- )\r
-{\r
- UINT32 SysCfgCtrl;\r
-\r
- if (EfiAtRuntime ()) {\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- // Clear the COMPLETE bit\r
- MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE);\r
-\r
- // If writing, then set the data value\r
- if(ReadWrite == SYS_CFGCTRL_WRITE) {\r
- MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data);\r
- }\r
-\r
- // Set the control value\r
- SysCfgCtrl = SYS_CFGCTRL_START | ReadWrite | SYS_CFGCTRL_FUNCTION(Function) | SYS_CFGCTRL_SITE(Site) |\r
- SYS_CFGCTRL_POSITION(Position) | SYS_CFGCTRL_DEVICE(Device);\r
- MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl);\r
-\r
- // Wait until the COMPLETE bit is set\r
- while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) == 0);\r
-\r
- // Check for errors\r
- if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) {\r
- return RETURN_DEVICE_ERROR;\r
- }\r
-\r
- // If reading then get the data value\r
- if(ReadWrite == SYS_CFGCTRL_READ) {\r
- *Data = MmioRead32(ARM_VE_SYS_CFGDATA_REG);\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigGet (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- OUT UINT32* Value\r
- )\r
-{\r
- UINT32 Site;\r
- UINT32 Position;\r
- UINT32 Device;\r
-\r
- Position = 0;\r
- Device = 0;\r
-\r
- // Intercept some functions\r
- switch(Function) {\r
-\r
- case SYS_CFG_OSC_SITE1:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_1_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC_SITE2:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_2_SITE;\r
- break;\r
-\r
- case SYS_CFG_MUXFPGA:\r
- Site = *Value;\r
- break;\r
-\r
- case SYS_CFG_OSC:\r
- case SYS_CFG_VOLT:\r
- case SYS_CFG_AMP:\r
- case SYS_CFG_TEMP:\r
- case SYS_CFG_RESET:\r
- case SYS_CFG_SCC:\r
- case SYS_CFG_DVIMODE:\r
- case SYS_CFG_POWER:\r
- Site = ARM_VE_MOTHERBOARD_SITE;\r
- break;\r
-\r
- case SYS_CFG_SHUTDOWN:\r
- case SYS_CFG_REBOOT:\r
- case SYS_CFG_RTC:\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return AccessSysCfgRegister (SYS_CFGCTRL_READ, Function, Site, Position, Device, Value);\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigGetValues (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- IN UINTN Size,\r
- OUT UINT32* Values\r
- )\r
-{\r
- return RETURN_UNSUPPORTED;\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigSet (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- IN UINT32 Value\r
- )\r
-{\r
- UINT32 Site;\r
- UINT32 Position;\r
- UINT32 Device;\r
-\r
- Position = 0;\r
- Device = 0;\r
-\r
- // Intercept some functions\r
- switch(Function) {\r
-\r
- case SYS_CFG_OSC_SITE1:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_1_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC_SITE2:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_2_SITE;\r
- break;\r
-\r
- case SYS_CFG_MUXFPGA:\r
- Site = Value;\r
- break;\r
-\r
- case SYS_CFG_RESET:\r
- case SYS_CFG_SCC:\r
- case SYS_CFG_SHUTDOWN:\r
- case SYS_CFG_REBOOT:\r
- case SYS_CFG_DVIMODE:\r
- case SYS_CFG_POWER:\r
- Site = ARM_VE_MOTHERBOARD_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC:\r
- case SYS_CFG_VOLT:\r
- case SYS_CFG_AMP:\r
- case SYS_CFG_TEMP:\r
- case SYS_CFG_RTC:\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);\r
-}\r
-\r
-RETURN_STATUS\r
-ArmPlatformSysConfigSetDevice (\r
- IN SYS_CONFIG_FUNCTION Function,\r
- IN UINT32 Device,\r
- IN UINT32 Value\r
- )\r
-{\r
- UINT32 Site;\r
- UINT32 Position;\r
-\r
- Position = 0;\r
-\r
- // Intercept some functions\r
- switch(Function) {\r
- case SYS_CFG_SCC:\r
-#ifdef ARM_VE_SCC_BASE\r
- if (EfiAtRuntime ()) {\r
- return RETURN_UNSUPPORTED;\r
- }\r
- MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value);\r
- return RETURN_SUCCESS;\r
-#else\r
- // There is no System Configuration Controller on the Model\r
- return RETURN_UNSUPPORTED;\r
-#endif\r
-\r
- case SYS_CFG_OSC_SITE1:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_1_SITE;\r
- break;\r
-\r
- case SYS_CFG_OSC_SITE2:\r
- Function = SYS_CFG_OSC;\r
- Site = ARM_VE_DAUGHTERBOARD_2_SITE;\r
- break;\r
-\r
- case SYS_CFG_MUXFPGA:\r
- Site = Value;\r
- break;\r
-\r
- case SYS_CFG_RTC:\r
- return RETURN_UNSUPPORTED;\r
- //break;\r
-\r
- case SYS_CFG_OSC:\r
- case SYS_CFG_VOLT:\r
- case SYS_CFG_AMP:\r
- case SYS_CFG_TEMP:\r
- case SYS_CFG_RESET:\r
- case SYS_CFG_SHUTDOWN:\r
- case SYS_CFG_REBOOT:\r
- case SYS_CFG_DVIMODE:\r
- case SYS_CFG_POWER:\r
- Site = ARM_VE_MOTHERBOARD_SITE;\r
- break;\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for ArmVExpressSysConfigRuntimeLib module\r
-#\r
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-# Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVExpressSysConfigRuntimeLib\r
- FILE_GUID = 6275b819-615c-4a36-814a-c1f330b4e5d9\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformSysConfigLib|DXE_RUNTIME_DRIVER\r
-\r
-[Sources.common]\r
- ArmVExpressSysConfigRuntimeLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- IoLib\r
- UefiRuntimeLib\r
+++ /dev/null
-/**\r
-\r
- Copyright (c) 2012, ARM Ltd. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Library/ArmPlatformSysConfigLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DxeServicesTableLib.h>\r
-#include <Library/LcdPlatformLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-\r
-#include <Protocol/EdidDiscovered.h>\r
-#include <Protocol/EdidActive.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-typedef struct {\r
- UINT32 Mode;\r
- UINT32 HorizontalResolution;\r
- UINT32 VerticalResolution;\r
- LCD_BPP Bpp;\r
- UINT32 OscFreq;\r
-\r
- // These are used by HDLCD\r
- UINT32 HSync;\r
- UINT32 HBackPorch;\r
- UINT32 HFrontPorch;\r
- UINT32 VSync;\r
- UINT32 VBackPorch;\r
- UINT32 VFrontPorch;\r
-} LCD_RESOLUTION;\r
-\r
-\r
-LCD_RESOLUTION mResolutions[] = {\r
- { // Mode 0 : VGA : 640 x 480 x 24 bpp\r
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,\r
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
- },\r
- { // Mode 1 : SVGA : 800 x 600 x 24 bpp\r
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,\r
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
- },\r
- { // Mode 2 : XGA : 1024 x 768 x 24 bpp\r
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,\r
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
- },\r
- { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp\r
- SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),\r
- SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,\r
- SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH\r
- },\r
- { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp\r
- UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),\r
- UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,\r
- UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH\r
- },\r
- { // Mode 5 : HD : 1920 x 1080 x 24 bpp\r
- HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),\r
- HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,\r
- HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH\r
- }\r
-};\r
-\r
-EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {\r
- 0,\r
- NULL\r
-};\r
-\r
-EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {\r
- 0,\r
- NULL\r
-};\r
-\r
-EFI_STATUS\r
-LcdPlatformInitializeDisplay (\r
- IN EFI_HANDLE Handle\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard\r
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- // Install the EDID Protocols\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &Handle,\r
- &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,\r
- &gEfiEdidActiveProtocolGuid, &mEdidActive,\r
- NULL\r
- );\r
-\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformGetVram (\r
- OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
- OUT UINTN* VramSize\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_ALLOCATE_TYPE AllocationType;\r
-\r
- // Set the vram size\r
- *VramSize = LCD_VRAM_SIZE;\r
-\r
- *VramBaseAddress = (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE;\r
-\r
- // Allocate the VRAM from the DRAM so that nobody else uses it.\r
- if (*VramBaseAddress == 0) {\r
- AllocationType = AllocateAnyPages;\r
- } else {\r
- AllocationType = AllocateAddress;\r
- }\r
- Status = gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable.\r
- Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize,\r
- EFI_MEMORY_WC);\r
- ASSERT_EFI_ERROR(Status);\r
- if (EFI_ERROR(Status)) {\r
- gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize));\r
- return Status;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-UINT32\r
-LcdPlatformGetMaxMode (\r
- VOID\r
- )\r
-{\r
- //\r
- // The following line will report correctly the total number of graphics modes\r
- // that could be supported by the graphics driver:\r
- //\r
- return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION));\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformSetMode (\r
- IN UINT32 ModeNumber\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- // Set the video mode oscillator\r
- do {\r
- Status = ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq);\r
- } while (Status == EFI_TIMEOUT);\r
- if (EFI_ERROR(Status)) {\r
- ASSERT_EFI_ERROR (Status);\r
- return Status;\r
- }\r
-\r
- // Set the DVI into the new mode\r
- do {\r
- Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);\r
- } while (Status == EFI_TIMEOUT);\r
- if (EFI_ERROR(Status)) {\r
- ASSERT_EFI_ERROR (Status);\r
- return Status;\r
- }\r
-\r
- // Set the multiplexer\r
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);\r
- if (EFI_ERROR(Status)) {\r
- ASSERT_EFI_ERROR (Status);\r
- return Status;\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformQueryMode (\r
- IN UINT32 ModeNumber,\r
- OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
- )\r
-{\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Info->Version = 0;\r
- Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r
- Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r
- Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r
-\r
- switch (mResolutions[ModeNumber].Bpp) {\r
- case LCD_BITS_PER_PIXEL_24:\r
- Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r
- Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;\r
- Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;\r
- Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;\r
- Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r
- break;\r
-\r
- case LCD_BITS_PER_PIXEL_16_555:\r
- case LCD_BITS_PER_PIXEL_16_565:\r
- case LCD_BITS_PER_PIXEL_12_444:\r
- case LCD_BITS_PER_PIXEL_8:\r
- case LCD_BITS_PER_PIXEL_4:\r
- case LCD_BITS_PER_PIXEL_2:\r
- case LCD_BITS_PER_PIXEL_1:\r
- default:\r
- // These are not supported\r
- ASSERT(FALSE);\r
- break;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformGetTimings (\r
- IN UINT32 ModeNumber,\r
- OUT UINT32* HRes,\r
- OUT UINT32* HSync,\r
- OUT UINT32* HBackPorch,\r
- OUT UINT32* HFrontPorch,\r
- OUT UINT32* VRes,\r
- OUT UINT32* VSync,\r
- OUT UINT32* VBackPorch,\r
- OUT UINT32* VFrontPorch\r
- )\r
-{\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- *HRes = mResolutions[ModeNumber].HorizontalResolution;\r
- *HSync = mResolutions[ModeNumber].HSync;\r
- *HBackPorch = mResolutions[ModeNumber].HBackPorch;\r
- *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;\r
- *VRes = mResolutions[ModeNumber].VerticalResolution;\r
- *VSync = mResolutions[ModeNumber].VSync;\r
- *VBackPorch = mResolutions[ModeNumber].VBackPorch;\r
- *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformGetBpp (\r
- IN UINT32 ModeNumber,\r
- OUT LCD_BPP * Bpp\r
- )\r
-{\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- *Bpp = mResolutions[ModeNumber].Bpp;\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for HdLcdArmLib module\r
-#\r
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = HdLcdArmVExpress\r
- FILE_GUID = 535a720e-06c0-4bb9-b563-452216abbed4\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = LcdPlatformLib\r
-\r
-[Sources.common]\r
-\r
-HdLcdArmVExpress.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmPlatformSysConfigLib\r
- BaseLib\r
- DxeServicesTableLib\r
-\r
-[Protocols]\r
- gEfiEdidDiscoveredProtocolGuid # Produced\r
- gEfiEdidActiveProtocolGuid # Produced\r
-\r
-[Pcd]\r
- gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode\r
- gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Library/ArmPlatformSysConfigLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DxeServicesTableLib.h>\r
-#include <Library/LcdPlatformLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-\r
-#include <Protocol/EdidDiscovered.h>\r
-#include <Protocol/EdidActive.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-typedef struct {\r
- UINT32 Mode;\r
- UINT32 HorizontalResolution;\r
- UINT32 VerticalResolution;\r
- LCD_BPP Bpp;\r
- UINT32 OscFreq;\r
-\r
- UINT32 HSync;\r
- UINT32 HBackPorch;\r
- UINT32 HFrontPorch;\r
- UINT32 VSync;\r
- UINT32 VBackPorch;\r
- UINT32 VFrontPorch;\r
-} LCD_RESOLUTION;\r
-\r
-\r
-LCD_RESOLUTION mResolutions[] = {\r
- { // Mode 0 : VGA : 640 x 480 x 24 bpp\r
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,\r
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
- },\r
- { // Mode 1 : SVGA : 800 x 600 x 24 bpp\r
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,\r
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
- },\r
- { // Mode 2 : XGA : 1024 x 768 x 24 bpp\r
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,\r
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
- },\r
- { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp\r
- SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),\r
- SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,\r
- SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH\r
- },\r
- { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp\r
- UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),\r
- UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,\r
- UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH\r
- },\r
- { // Mode 5 : HD : 1920 x 1080 x 24 bpp\r
- HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),\r
- HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,\r
- HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH\r
- },\r
- { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)\r
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,\r
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
- },\r
- { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)\r
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,\r
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
- },\r
- { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)\r
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,\r
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
- },\r
- { // Mode 9 : VGA : 640 x 480 x 15 bpp\r
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,\r
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
- },\r
- { // Mode 10 : SVGA : 800 x 600 x 15 bpp\r
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,\r
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
- },\r
- { // Mode 11 : XGA : 1024 x 768 x 15 bpp\r
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,\r
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
- },\r
- { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings\r
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,\r
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
- },\r
- { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)\r
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,\r
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,\r
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH\r
- },\r
- { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)\r
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,\r
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,\r
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH\r
- },\r
- { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)\r
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,\r
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,\r
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH\r
- }\r
-};\r
-\r
-EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {\r
- 0,\r
- NULL\r
-};\r
-\r
-EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {\r
- 0,\r
- NULL\r
-};\r
-\r
-\r
-EFI_STATUS\r
-LcdPlatformInitializeDisplay (\r
- IN EFI_HANDLE Handle\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard\r
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);\r
- if (!EFI_ERROR(Status)) {\r
- // Install the EDID Protocols\r
- Status = gBS->InstallMultipleProtocolInterfaces(\r
- &Handle,\r
- &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,\r
- &gEfiEdidActiveProtocolGuid, &mEdidActive,\r
- NULL\r
- );\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformGetVram (\r
- OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
- OUT UINTN* VramSize\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- Status = EFI_SUCCESS;\r
-\r
- // Is it on the motherboard or on the daughterboard?\r
- switch(PL111_CLCD_SITE) {\r
-\r
- case ARM_VE_MOTHERBOARD_SITE:\r
- *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
- *VramSize = LCD_VRAM_SIZE;\r
- break;\r
-\r
- case ARM_VE_DAUGHTERBOARD_1_SITE:\r
- *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;\r
- *VramSize = LCD_VRAM_SIZE;\r
-\r
- // Allocate the VRAM from the DRAM so that nobody else uses it.\r
- Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable.\r
- Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize,\r
- EFI_MEMORY_WC);\r
- ASSERT_EFI_ERROR(Status);\r
- if (EFI_ERROR(Status)) {\r
- gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize));\r
- return Status;\r
- }\r
- break;\r
-\r
- default:\r
- // Unsupported site\r
- Status = EFI_UNSUPPORTED;\r
- break;\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-UINT32\r
-LcdPlatformGetMaxMode (\r
- VOID\r
- )\r
-{\r
- // The following line will report correctly the total number of graphics modes\r
- // supported by the PL111CLCD.\r
- //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1;\r
-\r
- // However, on some platforms it is desirable to ignore some graphics modes.\r
- // This could be because the specific implementation of PL111 has certain limitations.\r
-\r
- // Set the maximum mode allowed\r
- return (PcdGet32(PcdPL111LcdMaxMode));\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformSetMode (\r
- IN UINT32 ModeNumber\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT32 LcdSite;\r
- UINT32 OscillatorId;\r
- SYS_CONFIG_FUNCTION Function;\r
- UINT32 SysId;\r
-\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- LcdSite = PL111_CLCD_SITE;\r
-\r
- switch(LcdSite) {\r
- case ARM_VE_MOTHERBOARD_SITE:\r
- Function = SYS_CFG_OSC;\r
- OscillatorId = PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID;\r
- break;\r
- case ARM_VE_DAUGHTERBOARD_1_SITE:\r
- Function = SYS_CFG_OSC_SITE1;\r
- OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);\r
- break;\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- // Set the video mode oscillator\r
- Status = ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResolutions[ModeNumber].OscFreq);\r
- if (EFI_ERROR(Status)) {\r
- ASSERT_EFI_ERROR (Status);\r
- return Status;\r
- }\r
-\r
- // The FVP foundation model does not have an LCD.\r
- // On the FVP models the GIC variant in encoded in bits [15:12].\r
- // Note: The DVI Mode is not modelled by RTSM or FVP models.\r
- SysId = MmioRead32 (ARM_VE_SYS_ID_REG);\r
- if (SysId != ARM_RTSM_SYS_ID) {\r
- // Take out the FVP GIC variant to reduce the permutations.\r
- SysId &= ~ARM_FVP_SYS_ID_VARIANT_MASK;\r
- if (SysId != ARM_FVP_BASE_BOARD_SYS_ID) {\r
- // Set the DVI into the new mode\r
- Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);\r
- if (EFI_ERROR(Status)) {\r
- ASSERT_EFI_ERROR (Status);\r
- return Status;\r
- }\r
- }\r
- }\r
-\r
- // Set the multiplexer\r
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite);\r
- if (EFI_ERROR(Status)) {\r
- ASSERT_EFI_ERROR (Status);\r
- return Status;\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformQueryMode (\r
- IN UINT32 ModeNumber,\r
- OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
- )\r
-{\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- Info->Version = 0;\r
- Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;\r
- Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;\r
- Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;\r
-\r
- switch (mResolutions[ModeNumber].Bpp) {\r
- case LCD_BITS_PER_PIXEL_24:\r
- Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r
- Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;\r
- Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;\r
- Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;\r
- Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;\r
- break;\r
-\r
- case LCD_BITS_PER_PIXEL_16_555:\r
- case LCD_BITS_PER_PIXEL_16_565:\r
- case LCD_BITS_PER_PIXEL_12_444:\r
- case LCD_BITS_PER_PIXEL_8:\r
- case LCD_BITS_PER_PIXEL_4:\r
- case LCD_BITS_PER_PIXEL_2:\r
- case LCD_BITS_PER_PIXEL_1:\r
- default:\r
- // These are not supported\r
- ASSERT(FALSE);\r
- break;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformGetTimings (\r
- IN UINT32 ModeNumber,\r
- OUT UINT32* HRes,\r
- OUT UINT32* HSync,\r
- OUT UINT32* HBackPorch,\r
- OUT UINT32* HFrontPorch,\r
- OUT UINT32* VRes,\r
- OUT UINT32* VSync,\r
- OUT UINT32* VBackPorch,\r
- OUT UINT32* VFrontPorch\r
- )\r
-{\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- *HRes = mResolutions[ModeNumber].HorizontalResolution;\r
- *HSync = mResolutions[ModeNumber].HSync;\r
- *HBackPorch = mResolutions[ModeNumber].HBackPorch;\r
- *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;\r
- *VRes = mResolutions[ModeNumber].VerticalResolution;\r
- *VSync = mResolutions[ModeNumber].VSync;\r
- *VBackPorch = mResolutions[ModeNumber].VBackPorch;\r
- *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-LcdPlatformGetBpp (\r
- IN UINT32 ModeNumber,\r
- OUT LCD_BPP * Bpp\r
- )\r
-{\r
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- *Bpp = mResolutions[ModeNumber].Bpp;\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-#\r
-# Component description file for ArmVeGraphicsDxe module\r
-#\r
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL111LcdArmVExpressLib\r
- FILE_GUID = b7f06f20-496f-11e0-a8e8-0002a5d5c51b\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = LcdPlatformLib\r
-\r
-[Sources.common]\r
- PL111LcdArmVExpress.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmPlatformSysConfigLib\r
- BaseLib\r
- DxeServicesTableLib\r
-\r
-[Protocols]\r
- gEfiEdidDiscoveredProtocolGuid # Produced\r
- gEfiEdidActiveProtocolGuid # Produced\r
-\r
-[Pcd]\r
- gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode\r
- gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId\r
+++ /dev/null
-/** @file\r
- Template library implementation to support ResetSystem Runtime call.\r
-\r
- Fill in the templates with what ever makes you system reset.\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>\r
- Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-\r
-#include <Library/ArmPlatformSysConfigLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/ResetSystemLib.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-/**\r
- This function causes a system-wide reset (cold reset), in which\r
- all circuitry within the system returns to its initial state. This type of\r
- reset is asynchronous to system operation and operates without regard to\r
- cycle boundaries.\r
-\r
- If this function returns, it means that the system does not support cold\r
- reset.\r
-**/\r
-VOID\r
-EFIAPI\r
-ResetCold (\r
- VOID\r
- )\r
-{\r
- ArmPlatformSysConfigSet (SYS_CFG_REBOOT, 0);\r
-}\r
-\r
-/**\r
- This function causes a system-wide initialization (warm reset), in which all\r
- processors are set to their initial state. Pending cycles are not corrupted.\r
-\r
- If this function returns, it means that the system does not support warm\r
- reset.\r
-**/\r
-VOID\r
-EFIAPI\r
-ResetWarm (\r
- VOID\r
- )\r
-{\r
- ResetCold ();\r
-}\r
-\r
-/**\r
- This function causes the system to enter a power state equivalent\r
- to the ACPI G2/S5 or G3 states.\r
-\r
- If this function returns, it means that the system does not support shut down reset.\r
-**/\r
-VOID\r
-EFIAPI\r
-ResetShutdown (\r
- VOID\r
- )\r
-{\r
- ArmPlatformSysConfigSet (SYS_CFG_SHUTDOWN, 0);\r
-}\r
-\r
-/**\r
- This function causes the system to enter S3 and then wake up immediately.\r
-\r
- If this function returns, it means that the system does not support S3\r
- feature.\r
-**/\r
-VOID\r
-EFIAPI\r
-EnterS3WithImmediateWake (\r
- VOID\r
- )\r
-{\r
- // not implemented\r
-}\r
-\r
-/**\r
- This function causes a systemwide reset. The exact type of the reset is\r
- defined by the EFI_GUID that follows the Null-terminated Unicode string passed\r
- into ResetData. If the platform does not recognize the EFI_GUID in ResetData\r
- the platform must pick a supported reset type to perform.The platform may\r
- optionally log the parameters from any non-normal reset that occurs.\r
-\r
- @param[in] DataSize The size, in bytes, of ResetData.\r
- @param[in] ResetData The data buffer starts with a Null-terminated string,\r
- followed by the EFI_GUID.\r
-**/\r
-VOID\r
-EFIAPI\r
-ResetPlatformSpecific (\r
- IN UINTN DataSize,\r
- IN VOID *ResetData\r
- )\r
-{\r
- ResetCold ();\r
-}\r
+++ /dev/null
-#/** @file\r
-# Reset System lib to make it easy to port new platforms\r
-#\r
-# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmVeResetSystemLib\r
- FILE_GUID = 36885202-0854-4373-bfd2-95d229b44d44\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ResetSystemLib\r
-\r
-[Sources.common]\r
- ResetSystemLib.c\r
-\r
-[Packages]\r
- MdeModulePkg/MdeModulePkg.dec\r
- MdePkg/MdePkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- DebugLib\r
- ArmPlatformSysConfigLib\r
projects / mirror_edk2.git / commitdiff